WCH CH561Q

CH561 series MCUs are 32-bit RISC CPUs with a reduced instruction set. The instruction set is compatible with ARMv5TE, supporting 16-bit Thumb instructions and enhanced DSP instructions. The default system clock frequency is 100MHz, with a maximum of 130MHz. The highly integrated peripherals and high performance enable it to be widely used in various embedded applications.

The peripheral components of CH561 include up to 64K of FLASH memory, 32K of SRAM, 28K of DataFlash, 10/100Mbps Ethernet, 2 SPI interfaces, 2 UART interfaces, 1-channel 10-bit ADC, 4 general-purpose timers, 8-bit passive parallel interface, in-system programming (ISP) interface, and up to 27 general-purpose I/O pins.

• On-chip FLASH up to 64K for program code storage, with write protection, 100,000 erase/write cycles, 20-year data retention, and ICP/ISP upgrade support
• On-chip SRAM 32K for data buffering
• On-chip DataFlash 28K for non-volatile data storage
• Integrated MAC and DSP-based 10/100Base-TX Fast Ethernet transceiver (PHY), supporting 10/100Mbps twisted-pair network communication, compliant with IEEE 802.3, 802.3u and FDDI-TP-PMD, Wake-On-LAN support, independent 2K-byte TX/RX FIFOs, DMA support
• Factory-programmed IEEE-assigned unique MAC address per chip
• 2× SPI controllers (SPI0, SPI1) with adjustable speed up to half of system clock SCLK (~50MHz), simplex I/O multiplexing support; SPI0 supports Master/Slave mode, 32-level FIFO, DMA; SPI1 supports Master mode only, 16-level FIFO
• 2× 16C550-compatible asynchronous UART controllers with adjustable speed up to 1/8 of system clock SCLK (~16Mbps); one supports full Modem signals, 16-level FIFO; the other supports CTS/RTS only but features automatic bus address comparison in 9-bit serial mode, SIR/IrDA codec, and 32-level FIFO
• 1-channel 10-bit ADC with adjustable sample rate up to 1Msps, 8-level FIFO, interrupt trigger on configurable threshold, 2-channel auto-scan, software algorithm decoding, DMA support
• 4× 28-bit timers with input signal width measurement/capture (high/low/toggle), PWM output, 8-level FIFO; 3 of 4 support DMA
• Low-power sleep mode with wake-up via GPIO and other external sources
• 64-bit unique ID per chip for device identification or data encryption
• 27 GPIO pins; select pins support pull-up/pull-down resistors, Schmitt-trigger input, dual drive strength, and level/edge interrupts
• CPU operating voltage: 1.65–1.95V (1.8V±10%); I/O operating voltage: 3.0–3.6V (3.3V±10%); select I/O pins are 5V tolerant

• Highly integrated peripherals and high performance enable broad applicability across diverse embedded applications.