MICROCHIP ATSAMA5D35A-CN

The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM® Cortex®-A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I²C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its low power consumption levels make the SAMA5D3 particularly suited for battery-powered devices.

• Core
  • ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set
  • CPU Frequency up to 536 MHz
  • 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)
  • Fully Integrated MMU and Floating Point Unit (VFPv4)
• Memories
  • One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order
  • One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed
  • High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC)
• System running up to 166 MHz
  • Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock
  • Boot Mode Select Option, Remap Command
  • Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator
  • Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
  • One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed
  • 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers
  • 64-bit Advanced Interrupt Controller
  • Three Programmable External Clock Signals
  • Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer
  • Shut Down Controller
  • Battery Backup Registers
  • Clock Generator and Power Management Controller
  • Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
  • LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion
  • ITU-R BT. 601/656 Image Sensor Interface
  • Three HS/FS/LS USB Ports with On-Chip Transceivers
  • One Device Controller
  • One Host Controller with Integrated Root Hub (3 Downstream Ports)
  • One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support
  • One 10/100 Mbps Ethernet MAC Controller (EMAC)
  • Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B
  • Softmodem Interface
  • Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)
  • Two Master/Slave Serial Peripheral Interfaces
  • Two Synchronous Serial Controllers
  • Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS
  • Four USARTs, two UARTs, one DBGU
  • Two Three-channel 32-bit Timer/Counters
  • One 4-channel 16-bit PWM Controller
  • One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function
• Safety
  • Power-on Reset Cells
  • Independent Watchdog
  • Main Crystal Clock Failure Detection
  • Write Protection Registers
  • SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) Memory Management Unit
  • TRNG: True Random Number Generator
  • Encryption Engine
    • AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
    • TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications
  • Atmel® Secure Boot Solution
• I/O
  • Five 32-bit Parallel Input/Output Controllers
  • 160 I/Os
  • Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input
  • Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering
  • Slew Rate Control on High Speed I/Os
  • Impedance Control on DDR I/Os

• control panel/HMI applications
• applications that require high levels of connectivity in the industrial and consumer markets
• battery-powered devices