Rochester Electronics 54F163/B2A

Rochester-branded components are manufactured using die/wafers purchased from original suppliers or Rochester-fabricated wafers produced under original intellectual property. All re-manufacturing is performed with approval from the original component manufacturer (OCM). Parts are tested using original factory test programs or Rochester-developed test solutions to ensure products meet or exceed OCM datasheet requirements. Rochester Electronics, LLC is committed to providing products that meet customer quality expectations, with performance comparable to that originally offered by the industry manufacturer. The datasheet from the original manufacturer accompanying this document reflects the performance and specifications of the Rochester-manufactured version of this device. Rochester Electronics guarantees that its semiconductor products perform in accordance with original OCM specifications. "Typical" values are provided for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing.

• Supply voltage range: -0.5 V DC to +7.0 V DC
• Input voltage range: -1.2 V DC (at -18 mA) to +7.0 V DC
• Storage temperature range: -65°C to +150°C
• Maximum power dissipation per device (PD): 303 mW for device types 01, 02, 03, 04
• Lead temperature (soldering, 10 seconds): +300°C
• Junction-to-case thermal resistance (θJC): (refer to MIL-STD-1835)
• Junction temperature (TJ): 175°C
• Recommended supply voltage (VCC): 4.5 V DC min to 5.5 V DC max
• Minimum HIGH-level input voltage (VIH): 2.0 V DC
• Maximum LOW-level input voltage (VIL): 0.8 V DC
• Normalized fan-out (per output): 33 max at LOW logic level, 50 max at HIGH logic level
• Case operating temperature range (TC): -55°C to +125°C
• Clock pulse HIGH width (P̄E = HIGH, device types 01, 02): 9.0 ns min
• Clock pulse HIGH width (PE = LOW, device types 01, 02): 7.0 ns min
• Clock pulse LOW width (P̄E = HIGH, device types 01, 02): 8.0 ns min
• Clock pulse LOW width (PE = LOW, device types 01, 02): 9.0 ns min
• Master reset pulse LOW width (MR = LOW, device type 01): 9.5 ns min
• PL pulse LOW width: 8.5 ns min for device type 03, 7.5 ns min for device type 04
• Clock pulse LOW width (device type 03): 7.0 ns min
• CPU or CPD pulse LOW width (device type 04): 7.0 ns min
• Master reset pulse HIGH width (MR = HIGH, device type 04): 6.0 ns min
• CPU or CPD pulse LOW width (direction change, device type 04): 12.0 ns min
• Pn HIGH to clock pulse setup time (device types 01, 02): 5.5 ns min
• Pn LOW to clock pulse setup time (device types 01, 02): 5.5 ns min
• PE or SR HIGH to clock pulse setup time (device types 01, 02): 13.5 ns min
• PE or SR LOW to clock pulse setup time (device types 01, 02): 10.5 ns min
• CEP or CET HIGH to clock pulse setup time (device types 01, 02): 13.0 ns min
• CEP or CET LOW to clock pulse setup time (device types 01, 02): 7.5 ns min
• Ū/D HIGH to clock pulse setup time (device type 03): 12.0 ns min
• Ū/D LOW to clock pulse setup time (device type 03): 12.0 ns min
• Pn HIGH to PL setup time (device types 03, 04): 6.0 ns min
• Pn LOW to PL setup time (device types 03, 04): 6.0 ns min
• CE LOW to clock pulse setup time (device type 03): 10.5 ns min
• Pn HIGH to clock pulse hold time (device types 01, 02): 2.5 ns min
• Pn LOW to clock pulse hold time (device types 01, 02): 2.5 ns min
• P̄E or S̄R HIGH to clock pulse hold time (device types 01, 02): 2.0 ns min
• P̄E or S̄R LOW to clock pulse hold time (device types 01, 02): 0.0 ns min
• CEP or CET HIGH to clock pulse hold time (device types 01, 02): 2.0 ns min
• CEP or CET LOW to clock pulse hold time (device types 01, 02): 2.0 ns min