TI DM54S139J/883

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The S138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The S139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

• Designed specifically for high speed: Memory decoders Data transmission systems
• S138 3-to-8-line decoders incorporates 3 enable inputs to simplity cascading and/or data reception
• S139 contains two fully independent 2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay time (3 levels of logic) S138 8ns S139 7.5 ns
• Typical power dissipation S138 245 mW S139 300 mW