Infineon/CYPRESS CY23FS08OC

CY23FS08 is a FailSafe zero-delay buffer featuring two reference clock inputs and eight phase-aligned outputs. This device provides an optimized solution for applications requiring continuous operation during a primary clock failure. Continuous, glitch-free operation is achieved using a DCXO, which serves as a redundant clock source during reference clock failure, retaining the last frequency and phase information of the reference clock. What makes the CY23FS08 unique is that the DCXO is actually the primary clock source, synchronized (phase-aligned) to the external reference clock. When the external clock is restored, the DCXO automatically resynchronizes to it. The crystal frequency connected to the DCXO must be selected as an integer multiple of the reference clock frequency. This multiple is set by four selection lines S[4:1]. The CY23FS08 has three separate power supplies: one for the core, one for Bank A outputs, and one for Bank B outputs. Each output supply, except VDDC, can be connected to either 2.5V or 3.3V. VDDC is the power pin for internal circuitry and must be connected to 3.3V.

• Internal DCXO for continuous glitch-free operation
• Zero input-to-output propagation delay
• 100 ps typical output cycle-to-cycle jitter
• 110 ps typical output-to-output skew
• 1 MHz–200 MHz reference input
• Industry-standard input crystal support
• 200 MHz (commercial), 166 MHz (industrial) output
• 5V-tolerant inputs
• PLL bypass mode
• Dual reference inputs
• 28-pin SSOP
• Separate 2.5V or 3.3V output supply
• 3.3V core supply
• Industrial temperature available

• Clock distribution applications