Infineon/CYPRESS CY7C144-55JCT

The CY7C144 and CY7C145 are high-speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Multiple arbitration schemes are incorporated to handle simultaneous access to the same data by multiple processors. Two ports are provided to allow independent, asynchronous read and write access to any location in memory. They can be used as standalone 64/72-Kbit dual-port static RAMs, or multiple devices can be combined for 16/18-bit or wider master/slave dual-port static RAM configurations. An M/S pin is provided to support 16/18-bit or wider memory applications without the need for separate master/slave devices or additional discrete logic.

• True dual-port memory cell with simultaneous read access to the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65 micron CMOS for speed and power
• High-speed access: 15 ns
• Low active power dissipation: ICC = 160 mA (max)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/slave select pin for bus width expansion to 16/18 bits or wider
• Busy arbitration scheme
• Semaphores for inter-port software handshaking
• Interrupt flags for inter-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP packages
• Lead-free packages available

• Inter-processor/multi-processor designs
• Communication status buffering
• Dual-port video/graphics memory