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TI 74AC16244DGGR product image
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TI 74AC16244DGGRRoHS

Hersteller
TI
Herst.-Teilenr.
74AC16244DGGR
LCSC-Nr.
C2675931
Verp.
TSSOP-48-6.1mm
Kundennummer
Hauptmerkm.
16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
Datenblattpdf iconTI 74AC16244DGGR
Vorrätig: 6
6 Ab Lager, sofort versandfertig
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-PreisGesamtbetrag
1+$ 2.2509$ 2.25
10+$ 1.8918$ 18.92
30+$ 1.6678$ 50.03
100+$ 1.4377$ 143.77
500+$ 1.3334$ 666.70
1,000+$ 1.2889$ 1288.90
Standardgehäuse2000/Full Reel
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
HerstellerTI
Verp.TSSOP-48-6.1mm
Input type-
Current - Output High(IOH)24mA
Series74AC
Voltage - Supply3V~5.5V
Output TypeTri-State
Current - Output Low(IOL)24mA
Number of Bits per Element4
Channel TypeUnidirectional
FeaturesOutput enable
Number of Elements4
Propagation Delay4.6ns@5V,50pF
Quiescent Current80uA
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Beschreibung

KI-Übersetzung

The ’AC16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. When OC(overline) is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The 74AC16244 is packaged in the TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

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KI-Übersetzung
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed Vcc and GND Configuration Minimizes High-Speed Switching Noise
  • EPIC (Enhanced-Performance Implanted CMOS) 1- II' [μm] Process
  • 500 - mA Typical Latch-Up Immunity at 125℃
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings