LCSC Electronics logoLCSC Electronics svg logo
Accedi
USD
Carrello
MICROCHIP ZL30614LDG6 product image
Immagini a scopo illustrativo

MICROCHIP ZL30614LDG6

Produttore
MICROCHIP
Cod. Prod.
ZL30614LDG6
Cod. LCSC
C1542292
Imballo
aQFN-100(10x10)
Numero Cliente
Attr. chiave
aQFN-100(10x10) Application Specific Clock/Timing RoHS
Scheda Tecnicapdf iconMICROCHIP ZL30614LDG6
Conformità RoHS1 documenti disponibili
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 53.6726$ 53.67
200+$ 20.7711$ 4154.22
500+$ 20.0418$ 10020.90
1,000+$ 19.6804$ 19680.40
Package Standard240/Full Tray
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing
ProduttoreMICROCHIP
ImballoaQFN-100(10x10)
FeaturesTimestamp function;Programmable clock output;Non-volatile parameter storage
Segnala un erroreMostra prodotti simili (0) >

Caratteristiche

Traduzione AI
  • Up to four independent clock channels
  • Excellent jitter performance of 180 fs rms in 12 kHz to 20 MHz band meets jitter requirements of 10G/40G and 100G PHYs
  • Three programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 900 MHz
  • One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
  • 6 differential (CML) or 12 single ended (CMOS) ultralow jitter outputs plus two general purpose CMOS outputs
  • Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
  • Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
  • Up to four programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 1 kHz to 900 MHz and to clock plus sync pulse
  • Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 1 ppb with post holdover filter
  • Operates from a single crystal resonator or clock oscillator
  • Configurable from SPI/I2C bus or from pre-configured flash memory
  • Accepts up to 10 LVCMOS or 5 LVDS/HCSL/LVPECL/CML inputs
  • Frequencies from 0.5 Hz to 180 MHz for LVCMOS
  • Frequencies from 0.5 Hz to 900 MHz for LVDS/HCSL/LVPECL/CML
  • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
  • Each input reference has its own set of monitors which can be independently programmed
  • Loss of signal (LOS)
  • Single Cycle Monitor (Triggers on glitches or variation in duty-cycle)
  • Coarse Frequency Monitor
  • Precise Frequency Monitor
  • Locks to gapped clocks
  • Supports 64 kHz composite clocks with external glue logic
  • Supports embedded pulse per second (ePPS) single wire for carrying high-speed clock & 1PPS
  • Supports REF-SYNC pair, a combination of a high speed clock reference and a frame pulse sync pair
  • Each output can generate clock, sync pulse, embedded pulse per second (ePPS) or embedded pulse per 2 seconds (ePP2S)
  • Clock modulated sync feature helps in reducing number of clock lines on backplane and in addition provides equal delay for both clock and sync signals
  • Digital PLLs filter jitter from 14 Hz up to 470 Hz
  • Multiple modes of operation: Freerun, Forced holdover, Forced reference, Automatic, NCO
  • Internal state machine automatically controls state: Locked, Acquiring, Holdover
  • Support for fast lock with lock times in seconds
  • Support for hitless reference switching
  • Internal, per DPLL, time of day counters maintaining full 48-bit seconds and 32-bit nanoseconds aligned to 1PPS rollover
  • Holdover better than 0.01 ppb
  • Full rate conversion between input and output clock frequencies
  • Supports ITU-T G.823, G.824 and G.8261 for 2048 Kbit/s and 1544 Kbit/s interfaces
  • Supports G.781 SETS
  • Four programmable synthesizers
  • Precision Synthesizers: Each ultra-low jitter output can be independently set to be differential (CML) or two CMOS
  • Six CML outputs: Generate clock rates from 0.5 Hz to 900 MHz, Jitter performance of 180 fs rms (12 KHz – 20 MHz), Meets OC-192, STM-64, 1 GbE & 10 GbE interface jitter requirements
  • Twelve LVCMOS outputs: Generate clock rates from 0.5 Hz to 180 MHz, Jitter performance of 290 fs rms (12 kHz – 20 MHz)
  • General Synthesizer: Two LVCMOS outputs, Generate clock rates from 1 Hz to 180 MHz, Jitter performance of 17 ps rms (12 kHz – 20 MHz)
  • Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
  • Each output has its own power supply pin which can be hooked to 3.3V, 2.5V or 1.8V supplies. Outputs may be disabled to save power

Applicazioni

Traduzione AI
  • Synchronous Ethernet/Sonet/SDH timing and line cards
  • Wireless Backhaul
  • Wireless Base stations
  • Test Equipment
  • Integrated basestation reference synchronization for air interfaces for GSM, WCDMA, TD-SCDMA, LTE and LTE-A FDD or TDD mobile technology
  • femtocells, small cells (residential, urban, rural, enterprise), picocells and macrocells
  • Mobile Backhaul NID, cell-site router, edge switch/router, microwave or access aggregation node
  • EPON/GPON OLT and ONU/OLT
  • DSLAM and RT-DSLAM
  • 10 Gigabit line cards
  • Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W
  • SONET/SDH, Fiber Channel, XAUI