Infineon/CYPRESS CY7C1353B-66AC

CY7C1353B is a 3.3V, 256K×18 synchronous flow-through burst SRAM designed to support unlimited consecutive read and write operations without wait states. The device incorporates advanced No Bus Latency (NoBL™) logic to transfer data every clock cycle, enabling continuous read/write operations and significantly improving SRAM data throughput — particularly suited for systems requiring frequent write-to-read transitions. It is pin and function compatible with ZBT SRAMs MCM63Z819 and MT55L256L18F. All synchronous inputs pass through input registers clocked by the rising edge of the clock. The clock input is qualified by a Clock Enable (CEN) signal; when CEN is deasserted, operation is suspended and the previous clock cycle is extended. Maximum access latency from the rising clock edge is 7.5 ns (117 MHz device). Write operations are controlled by four Byte Write Selects (BWS[1:0]) and a Write Enable (WE) input; all writes are performed through an on-chip synchronous self-timed write circuit. Three synchronous chip enables (CE1, CE2, CE3) and one asynchronous Output Enable (OE) facilitate bank selection and output tristate control. To prevent bus contention, the output drivers synchronously enter tristate during the data phase of a write sequence.

• Pin-compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F
• Supports 117 MHz bus operation, zero wait states, data transfer every clock cycle
• Internal self-timed output buffer control, OE not required
• Registered inputs for flow-through operation
• Byte write capability
• 256K×18 universal I/O architecture
• Single 3.3V supply
• Fast clock-to-output time: 7.5 ns at 117 MHz; 8.5 ns at 100 MHz; 11.0 ns at 66 MHz; 12.0 ns at 50 MHz; 14.0 ns at 40 MHz
• Clock Enable (CEN) pin for operation pause
• Synchronous self-timed write
• Asynchronous output enable
• JEDEC standard 100-pin TQFP package
• Burst capability — linear or interleaved burst order
• Low standby power consumption