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MXIC MX29F800CBTI-70GTR product image
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MXIC MX29F800CBTI-70GTR

Manufacturer
MXIC
MPN
MX29F800CBTI-70GTR
LCSC Part #
C2803075
Packaging
TSOP-48
Customer #
Key Attributes
8Mbit 4.5V~5.5V 5MHz Parallel TSOP-48 Memory RoHS
DatasheetMXIC MX29F800CBTI-70GTR
Alternative Parts2
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerMXIC
PackagingTSOP-48
Operating Temperature-40℃~+85℃
FeaturesHardware Write Protection;Power-on reset
Memory Size8Mbit
Voltage - Supply4.5V~5.5V
Program / Erase Cycles100,000 cycles
Clock Frequency5MHz
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Write Cycle Time(tWC)-
Page Programming Time (Tpp)-
InterfaceParallel
Standby Supply Current1uA
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Features

AI Translation
  • Single power supply operation
  • Read, erase, and program operating voltage: 4.5 to 5.5V
  • 1,048,576 x 8 / 524,288 x 16 switchable
  • Boot sector architecture
  • T represents top boot sector
  • B represents bottom boot sector
  • Sector structure: 16K bytes x 1, 8K bytes x 2, 32K bytes x 1, 64K bytes x 15
  • Sector protection: hardware-based disable of program or erase operations for any combination of sectors
  • Temporary sector unprotect allows code changes to previously locked sectors
  • Latch-up immunity: 100 mA, voltage range from -1V to Vcc + 1V
  • JEDEC compliant
  • Pin and software compatible with single power supply flash memory
  • Access time: 70ns
  • Byte/word program time: 9us/11us (typical)
  • Erase time: 0.7s/sector, 8s/chip (typical)
  • Low power consumption
  • Low active read current: 40 mA (max) @ 5 MHz
  • Low standby current: 1uA (typical)
  • Minimum 100,000 erase/program cycles
  • 20-year data retention
  • Erase suspend/erase resume
  • Suspend sector erase operation to read or program data from/to another non-erased sector
  • Status reply: Data# polling and toggle bit provide detection of program and erase operation completion
  • RY/BY# output: hardware method for detecting program and erase operation completion
  • Hardware reset input: hardware method for resetting the internal state machine to read mode
  • 44-pin SOP package
  • 48-pin TSOP package
  • 48-ball LFBGA package
  • All devices are RoHS compliant
  • All non-RoHS compliant devices are not recommended for new designs