onsemi MC100EP140DR2G
| Manufacturer | |
| MPN | MC100EP140DR2G |
| LCSC Part # | C903847 |
| Packaging | SOIC-8 |
| Customer # | |
| Key Attributes | 2GHz 3V~3.6V 2 SOIC-8 Clock Generators, PLLs, Frequency Synthesizers RoHS |
| Datasheet | onsemi MC100EP140DR2G |
| RoHS Compliance | 4 documents available |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | onsemi | |
| Packaging | SOIC-8 | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | - | |
| Output Frequency(Max) | 2GHz | |
| Voltage - Supply | 3V~3.6V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | onsemi | |
| Packaging | SOIC-8 | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | - | |
| Output Frequency(Max) | 2GHz | |
| Voltage - Supply | 3V~3.6V | |
| Period Jitter, Peak-to-Peak | -;- |
| Type | Description | |
|---|---|---|
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
Introduction
The MC100EP140 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to “compare” an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a VCO. The typical output amplitude of the EP140 is 400 mV, allowing faster switching time and greater bandwidth. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.
Features
- 500 ps Typical Propagation Delay
- Maximum Frequency >2.1 GHz Typical
- Fully Differential Internally
- Advanced High Band Output Swing of 400 mV
- Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
- Rise and Fall Time: 100 ps Typical
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
- Open Input Default State
- Pb−Free Packages are Available
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | onsemi | |
| Packaging | SOIC-8 | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | - | |
| Output Frequency(Max) | 2GHz | |
| Voltage - Supply | 3V~3.6V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | onsemi | |
| Packaging | SOIC-8 | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | - | |
| Output Frequency(Max) | 2GHz | |
| Voltage - Supply | 3V~3.6V | |
| Period Jitter, Peak-to-Peak | -;- |
| Type | Description | |
|---|---|---|
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
Introduction
The MC100EP140 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to “compare” an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a VCO. The typical output amplitude of the EP140 is 400 mV, allowing faster switching time and greater bandwidth. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.
Features
- 500 ps Typical Propagation Delay
- Maximum Frequency >2.1 GHz Typical
- Fully Differential Internally
- Advanced High Band Output Swing of 400 mV
- Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
- Rise and Fall Time: 100 ps Typical
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
- Open Input Default State
- Pb−Free Packages are Available
C903847 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

