NXP LPC2387FBD100K

The LPC2387 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation support, and integrates 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock frequency. For the critical performance demands of interrupt service routines and DSP algorithms, performance can be improved by up to 30% compared to Thumb mode. For applications with strict code size requirements, the optional 16-bit Thumb mode reduces code size by more than 30% with minimal performance penalty. The LPC2387 is suited for versatile serial communication applications. It integrates a 10/100 Ethernet MAC, a USB full-speed device with 4 kB endpoint RAM, four UARTs, two CAN channels, one SPI interface, two SSPs, three I2C interfaces, and one I2S interface. This combination of serial communication interfaces, together with an on-chip 4 MHz internal oscillator, 64 kB SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for USB and general-purpose use, and 2 kB battery-backed SRAM, makes the device well suited for communication gateways and protocol converters. Multiple 32-bit timers, an enhanced 10-bit ADC, a 10-bit DAC, a PWM unit, a CAN control unit, up to 70 fast GPIO lines, and up to 12 edge- or level-sensitive external interrupt pins make this microcontroller particularly suitable for industrial control and medical systems.

• ARM7TDMI-S processor, up to 72 MHz operating frequency
• On-chip 512 kB flash program memory with ISP and IAP capability, located on ARM local bus for high-performance CPU access
• 64 kB SRAM on ARM local bus for high-performance CPU access
• 16 kB SRAM for Ethernet interface, also usable as general-purpose SRAM
• 16 kB SRAM for general-purpose DMA, also accessible by USB
• Dual AHB system supporting simultaneous Ethernet DMA, USB DMA, and on-chip flash program execution without conflicts; bus bridge allows Ethernet DMA access to the other AHB subsystem
• VIC supporting up to 32 vectored interrupts
• On-chip GPDMA controller on AHB, compatible with SSP, I2S, SD/MMC interfaces, and memory-to-memory transfers
• Integrated Ethernet MAC with dedicated DMA controller on a separate AHB
• Integrated USB 2.0 device/host/OTG with on-chip PHY and dedicated DMA controller
• Four UARTs with fractional baud rate generation; one with modem control I/O, one with IrDA support, all with FIFO
• Integrated dual-channel CAN controller
• Integrated SPI controller
• Two SSP controllers with FIFO and multi-protocol capability; one can operate as an SPI port alternative, sharing interrupts and pins, compatible with GPDMA
• Three I2C bus interfaces: one open-drain, two with standard port pins
• Integrated I2S interface for digital audio input/output, compatible with GPDMA
• Integrated SD/MMC memory card interface
• 70 general-purpose I/O pins with configurable pull-up/pull-down resistors
• 10-bit ADC with 6-pin input multiplexing
• 10-bit DAC
• Four general-purpose timer/counters with a total of 8 capture inputs and 10 compare outputs; each timer block has one external count input
• One PWM/timer block for three-phase motor control, PWM with two external count inputs
• RTC with dedicated power supply pin; clock source selectable from RTC oscillator or APB clock
• 2 kB SRAM powered by RTC supply pin, retaining data when the rest of the chip is powered down
• WDT with clock source selectable from internal RC oscillator, RTC oscillator, or APB clock
• Standard ARM test/debug interface compatible with existing tools
• Embedded Trace Module for real-time tracing
• Single 3.3 V supply, operating range 3.0 V to 3.6 V
• Four low-power modes: Idle, Sleep, Power-down, and Deep power-down
• Four external interrupt inputs configurable as edge/level sensitive; all pins on Port 0 and Port 2 can serve as edge-sensitive interrupt sources
• Processor wake-up from Power-down mode via any interrupt that can operate in Power-down mode, including external interrupts, RTC interrupt, USB activity, and Ethernet wake-up interrupt
• Two independent power domains for fine-grained power consumption control based on required functionality
• Individual clock dividers per peripheral for further power reduction
• Brown-out detection with independent thresholds for interrupt and forced reset
• On-chip power-on reset
• On-chip crystal oscillator, operating range 1 MHz to 25 MHz
• 4 MHz internal RC oscillator, trimmed to 1% accuracy, optionally selectable as system clock; CAN and USB not supported when used as CPU clock
• Single-chip 16-bit/32-bit MCU
• On-chip PLL allowing CPU operation at maximum speed without a high-frequency crystal; driven by main oscillator, internal RC oscillator, or RTC oscillator
• Flexible pin function selection for expanded on-chip peripheral usage

• Industrial control
• Medical systems
• Protocol converters
• Communications