Zynalog ZGAD125S14

ZGAD125S14 is a single-channel, 14-bit, 125Msps ADC designed for digitizing high-frequency, wide dynamic range signals. This series offers 69dB SNR and 93dB SFDR, making it ideal for demanding signal chain applications. The 600MHz input bandwidth enables excellent performance even at high sampling frequencies. Latency is only six clock cycles. Static characteristics include a typical integral nonlinearity of ±1LSB and a typical differential nonlinearity of ±0.35LSB. The clock input can be driven by sinusoidal, PECL, LVDS, TTL, or CMOS differential signals. An optional clock duty cycle stabilizer allows full-speed, high-performance operation over a wide range of clock duty cycles. The analog signal input is internally a differential CMOS sample-and-hold circuit, which must be differentially driven using the common-mode voltage set by the VCM output pin — the VCM voltage nominal value is 0.435×VDD. The input differential voltage must be within 1.5V, with 180° phase difference between the two inputs. An RC low-pass filter is recommended at the analog input. At higher input frequencies, using a transmission line balun transformer provides better balance and reduces distortion. When using the internal reference, pull the SENSE pin up to VDD; the input signal range is then ±0.75V. When using an external reference, connect the SENSE pin to a reference voltage between 1.2V and 1.3V; the input signal range is then ±0.6V × SENSE. The quality of the sampling clock input significantly affects the ADC noise performance and should be routed as an analog signal. The clock signal is internally biased to 1.2V through an equivalent 10kΩ resistance. If the driver common-mode voltage is between 1.1V and 1.5V, the clock input can be driven directly; otherwise, a transformer or coupling capacitor is required. The peak input voltage must not exceed VDD+0.1V or fall below -0.1V. For optimal performance, clock jitter of less than 160fs is recommended.

• Sample rate: 10Msps ~ 125Msps
• 1.8V single supply
• Output: DDR LVDS
• Input range: 1.5Vpp
• SNR: 69dB
• SFDR: 93dB
• Full-power bandwidth: 600MHz
• Full-rate power consumption: 265mW
• Single-channel sampling
• Optional clock duty cycle stabilizer
• Power-saving low-power mode and sleep mode
• Configurable SPI serial interface (supports 1.8V ~ 3.6V)
• Package: QFN40
• Operating temperature: -40℃ ~ 85℃

• Signal Chain
• Test & Measurement Instruments
• Medical Equipment
• Video Equipment
• Cellular Base Stations
• LiDAR