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RENESAS 9DB433AGLFT
| Manufacturer | |
| MPN | 9DB433AGLFT |
| LCSC Part # | C7495060 |
| Packaging | TSSOP-28 |
| Customer # | |
| Key Attributes | FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1-3 |
| Datasheet |  RENESAS 9DB433AGLFT |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | RENESAS | |
| Packaging | TSSOP-28 | |
| Number of ports | 4 | |
| Voltage - Supply | - | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | 166MHz | |
| Operating Temperature | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | RENESAS | |
| Packaging | TSSOP-28 | |
| Number of ports | 4 |
| Type | Description | |
|---|---|---|
| Voltage - Supply | - | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | 166MHz | |
| Operating Temperature | - |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.
Features
AI Translation
- 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
- OE# pins; suitable for Express Card applications
- PLL or bypass mode; PLL can dejitter incoming clock
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible; tracks spreading input clock for low EMI
- SMBus interface; unused outputs can be disabled
- Supports undriven differential outputs in Power Down mode for power management
- 4 0.7V current-mode differential HCSL output pairs
- Supports zero delay buffer mode and fanout mode
- Selectable bandwidth
- 50–110MHz operation in PLL mode
- 5–166MHz operation in Bypass mode
Applications
AI Translation
- 4 output PCIe Gen1–3 zero-delay/fanout buffer
In-Stock: 300
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 3.9286 | $ 3.93 |
| 10+ | $ 3.3629 | $ 33.63 |
| 30+ | $ 3.0265 | $ 90.80 |
| 100+ | $ 2.6852 | $ 268.52 |
| 500+ | $ 2.5291 | $ 1264.55 |
| 1,000+ | $ 2.4576 | $ 2457.60 |
Standard Packaging5000/Full Reel | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | RENESAS | |
| Packaging | TSSOP-28 | |
| Number of ports | 4 | |
| Voltage - Supply | - | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | 166MHz | |
| Operating Temperature | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Manufacturer | RENESAS | |
| Packaging | TSSOP-28 | |
| Number of ports | 4 |
| Type | Description | |
|---|---|---|
| Voltage - Supply | - | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | 166MHz | |
| Operating Temperature | - |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.
Features
AI Translation
- 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
- OE# pins; suitable for Express Card applications
- PLL or bypass mode; PLL can dejitter incoming clock
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible; tracks spreading input clock for low EMI
- SMBus interface; unused outputs can be disabled
- Supports undriven differential outputs in Power Down mode for power management
- 4 0.7V current-mode differential HCSL output pairs
- Supports zero delay buffer mode and fanout mode
- Selectable bandwidth
- 50–110MHz operation in PLL mode
- 5–166MHz operation in Bypass mode
Applications
AI Translation
- 4 output PCIe Gen1–3 zero-delay/fanout buffer
C7495060 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |