MAXIM MAX3693ECJ+

The MAX3693 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a PECL output buffer, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/frequency detector, loop filter/amplifier, voltage-controlled oscillator, and prescaler). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data. The PLL synthesizes an internal 622Mbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3693 on the rising transition of the parallel-clock input signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622Mbps internal serial clock signal divided by four. The allowable PCLKO-to-PCLKI skew is 0 to +4ns. This defines a timing window at about the PCLKO rising edge, during which a PCLKI rising edge may occur.

• Single +3.3V Supply
• 155Mbps (4-bit-wide) Parallel to 622Mbps Serial Conversion
• Clock Synthesis for 622Mbps
• 215mW Power
• Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
• LVDS Parallel Clock and Data Inputs
• Differential 3.3V PECL Serial-Data Output

• 622Mbps SDH/SONET Transmission Systems
• 622Mbps ATM/SONET Access Nodes
• Add/Drop Multiplexers
• Digital Cross Connects