AMD XC6VLX195T-L1FFG1156C

Virtex-6 FPGAs are the programmable silicon foundation of targeted design platforms, integrating hardware and software components that enable designers to focus on innovation from the very beginning of the development cycle. Built on the third-generation ASMBL columnar architecture, the family comprises multiple distinct sub-families. This overview covers devices in the LXT, SXT, and HXT sub-families. Each sub-family offers a different mix of features to most efficiently address the needs of a wide range of advanced logic designs. In addition to high-performance logic fabric, Virtex-6 FPGAs incorporate numerous built-in system-level blocks. These features enable logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on advanced 40 nm copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. They provide optimal solutions for high-performance logic design, high-performance DSP design, and high-performance embedded system design, delivering unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

• Three sub-families: LXT FPGA (high-performance logic with advanced serial connectivity), SXT FPGA (highest signal processing capability with advanced serial connectivity), HXT FPGA (highest bandwidth serial connectivity)
• Cross sub-family compatibility; LXT and SXT devices are pin-compatible within the same package
• Advanced high-performance FPGA logic featuring true 6-input LUT technology, dual LUT5 option, LUT/dual flip-flop pairs, improved routing efficiency, 64-bit distributed LUT RAM option per 6-input LUT, SRL32/dual SRL16 option with registered outputs
• Robust mixed-mode clock manager providing zero-delay buffering, frequency synthesis, clock phase shifting, input jitter filtering, and phase-matched clock division
• 36 Kb block RAM/FIFO memory with true dual-port RAM support, programmable dual-port width up to 36 bits, simple dual-port width up to 72 bits
• Enhanced programmable FIFO logic with built-in optional error correction circuitry; each block independently usable as two 18 Kb blocks
• High-performance parallel SelectIO technology supporting 1.2V to 2.5V I/O operation, source-synchronous interfaces via ChipSync technology, digitally controlled impedance active termination
• Flexible fine-grained I/O banking supporting high-speed memory interfaces with integrated write leveling
• Advanced DSP48E1 slices featuring 25×18 two's complement multiplier/accumulator, optional pipelining, new optional pre-adder for filter applications, optional bitwise logic functions, dedicated cascade connections
• Flexible configuration options supporting SPI and parallel flash interfaces, multi-bitstream support with dedicated fallback reconfiguration logic, automatic bus width detection
• System monitor capability on all devices supporting on-chip/off-chip temperature and supply voltage monitoring; all monitored parameters accessible via JTAG
• Integrated interface block for PCI Express designs compliant with PCI Express Base Specification 2.0, supporting Gen1 and Gen2 rates, endpoint and root port capability, x1, x2, x4, or x8 lane configurations per block
• GTX transceivers: rates up to 6.6 Gb/s; data rates below 480 Mb/s supported via oversampling in FPGA logic
• GTH transceivers: rates from 2.488 Gb/s to over 11 Gb/s
• Integrated 10/100/1000 Mb/s Ethernet MAC block supporting 1000BASE-X PCS/PMA and SGMII using GTX transceivers; MII, GMII, and RGMII support using SelectIO technology resources; 2500 Mb/s support
• 40 nm copper CMOS process technology
• 1.0V core voltage (–1, –2, –3 speed grades only); lower-power 0.9V core voltage option available (–1L speed grade only)
• Flip-chip packaging with high signal integrity; standard or lead-free package options available