micron MT57V1MH18EF-6

This device features a high-speed, low-power CMOS design utilizing an advanced 6T CMOS process. It integrates an 18Mb SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by an input clock pair and are latched on the rising edge of the clock. Synchronous inputs include all addresses, all data inputs, active-low load, and read/write signals. Write data is registered on the rising edge of the clock. Read data is driven on the rising edge of the data clock if a data clock is provided, or on the rising edge of the input clock if no data clock is provided. Asynchronous inputs include impedance matching. Synchronous data outputs are closely matched to two echo clocks, which can be used as data receive clocks. An output data clock is also provided to maximize system clock synchronization and data synchronization flexibility. Additional write registers are integrated to enhance pipelined write cycles and reduce read-to-write turnaround time. Write cycles are self-timed. The device does not use an internal PLL, allowing it to enter a stopped-clock state for reduced power consumption without requiring lengthy restart times. Four pins are dedicated to JTAG test functionality. The JTAG circuit is used to serially shift data into the SRAM. In this test operation mode, JTAG inputs use standard I/O levels to shift data. The device can be used in HSTL systems by supplying an appropriate reference voltage. It is well suited for applications requiring ultra-fast data transfer via data-doubling mode. It is also suitable for applications that benefit from the cost advantages of pipelined CMOS SRAM and reduced read-to-write turnaround time. This SRAM operates from a 2.5V supply, with all inputs and outputs HSTL compatible. It is ideal for cache, networking, telecommunications, DSP, and other applications that benefit from extremely wide, high-speed data buses.

• Fast cycle time
• Pipelined, double data rate operation
• Single 2.5V ± 0.1V power supply
• Separate isolated output buffer supply
• Standard 1.5V to 1.8V (±0.1V) HSTL I/O
• User-selectable threshold via VREF
• HSTL programmable impedance outputs, synchronizable with optional double data clock
• Optional echo clock for flexible data capture synchronization
• JTAG boundary scan
• Fully static design for reduced standby power
• Clock suspend capability
• Common data input and data output
• Low control pin count
• Internal self-timed, registered late write cycle
• Linear burst sequence with 4-beat burst counter
• 13mm x 15mm, 1mm pitch, 11 x 15 array FBGA package
• Full data coherency with most recent data

• Cache
• Networking
• Telecom
• DSP