GSI Technology, Inc. GS8128218GB-250I

GS8128218/36 is a 150,994,944-bit high-performance synchronous SRAM with a 2-bit burst address counter. Although this type was originally developed to support secondary cache applications for high-performance CPUs, the device can now be used in synchronous SRAM applications ranging from DSP main memory to network chipset support. Address, data I/O, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and controlled by a positive edge-triggered clock input (CK). Output enable (G) and power-down control (ZZ) are asynchronous inputs. A burst cycle can be initiated by either the ADSP or ADSC input. In burst mode, subsequent burst addresses are generated internally and controlled by ADV. The burst address counter can be configured to count in either linear or interleaved order via the linear burst order (LBO) input. The burst function is not mandatory. A new address can be loaded every cycle without degrading device performance.

• FT pin for user-configurable flow-through or pipelined operation
• Selectable single-cycle or double-cycle deselect
• IEEE 1149.1 JTAG boundary scan compatible
• ZQ mode pin for user-selectable high or low output drive
• 2.5V +10%/-10% core power supply
• 3.3V +10%/-10% core power supply
• 2.5V or 3.3V I/O power supply
• LBO pin for linear or interleaved burst mode
• Internal input resistors on mode pins allow pins to float
• Default SCD x18 or x36 interleaved pipeline mode
• Byte write and/or global write operation
• Internal self-timed write cycle
• ZZ pin for automatic power-down
• RoHS-compliant 119-ball and 165-ball BGA packages

• Secondary cache applications supporting high-performance CPUs
• Synchronous SRAM applications
• DSP main memory
• Network chipset support