GSI Technology GS8662D20BGD-550I
| Manufacturer | GSI TechnologyAsian Brands |
| MPN | GS8662D20BGD-550I |
| LCSC Part # | C6954732 |
| Packaging | FPBGA-165(13x15) |
| Customer # | |
| Key Attributes | 72Mbit FPBGA-165(13x15) Memory RoHS |
| Datasheet | GSI Technology GS8662D20BGD-550I |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | 72Mbit | |
| Voltage - Supply | 1.7V~1.9V;- | |
| Access Time | - | |
| Standby Supply Current | - | |
| Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function |
| Type | Description | |
|---|---|---|
| Memory Size | 72Mbit | |
| Voltage - Supply | 1.7V~1.9V;- | |
| Access Time | - | |
| Standby Supply Current | - | |
| Interface | - |
Introduction
The GS8662D06/11/20/38BD comply with the SigmaQuad-II+ SRAM pin standard and are 75,497,472-bit (72Mb) separate I/O synchronous SRAMs. They are part of a low-power, low-voltage HSTL I/O SRAM family designed to operate at the speeds required for cost-effective, high-performance networking systems. From a system architecture perspective, separate I/O SRAMs are attractive in applications requiring alternating reads and writes — the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating read/write operations — but are less suitable for applications requiring multiple consecutive reads or writes, as burst read/write transfers in separate I/O SRAMs halve the RAM bandwidth.
Features
- 2.5-cycle clock latency
- Synchronous read/write interface
- Standard pinout and package compliant
- Double data rate interface
- Byte write control sampled at data input
- 4-burst read/write operation support
- On-die termination on data, byte write, and clock inputs
- Core supply voltage: 1.8V ±100 mV
- 1.5V or 1.8V HSTL interface support
- Pipelined read operation
- Fully coherent read/write pipeline
- ZQ pin for programmable output drive strength
- Data valid pin support
- IEEE 1149.1 JTAG boundary scan compatible
- 165-ball, 13 mm × 15 mm, 1 mm ball pitch BGA package
- RoHS-compliant 165-ball BGA package available
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 369.0451 | $ 369.05 |
| 195+ | $ 147.2514 | $ 28714.02 |
| 495+ | $ 142.3309 | $ 70453.80 |
| 1,005+ | $ 139.9008 | $ 140600.30 |
Standard Packaging15/Full Tray | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function | |
| Memory Size | 72Mbit | |
| Voltage - Supply | 1.7V~1.9V;- | |
| Access Time | - | |
| Standby Supply Current | - | |
| Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | GSI Technology | |
| Packaging | FPBGA-165(13x15) | |
| Operating Temperature | -40℃~+100℃ | |
| Features | Built-in delay-locked loop;Boundary scan (JTAG) function |
| Type | Description | |
|---|---|---|
| Memory Size | 72Mbit | |
| Voltage - Supply | 1.7V~1.9V;- | |
| Access Time | - | |
| Standby Supply Current | - | |
| Interface | - |
Introduction
The GS8662D06/11/20/38BD comply with the SigmaQuad-II+ SRAM pin standard and are 75,497,472-bit (72Mb) separate I/O synchronous SRAMs. They are part of a low-power, low-voltage HSTL I/O SRAM family designed to operate at the speeds required for cost-effective, high-performance networking systems. From a system architecture perspective, separate I/O SRAMs are attractive in applications requiring alternating reads and writes — the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating read/write operations — but are less suitable for applications requiring multiple consecutive reads or writes, as burst read/write transfers in separate I/O SRAMs halve the RAM bandwidth.
Features
- 2.5-cycle clock latency
- Synchronous read/write interface
- Standard pinout and package compliant
- Double data rate interface
- Byte write control sampled at data input
- 4-burst read/write operation support
- On-die termination on data, byte write, and clock inputs
- Core supply voltage: 1.8V ±100 mV
- 1.5V or 1.8V HSTL interface support
- Pipelined read operation
- Fully coherent read/write pipeline
- ZQ pin for programmable output drive strength
- Data valid pin support
- IEEE 1149.1 JTAG boundary scan compatible
- 165-ball, 13 mm × 15 mm, 1 mm ball pitch BGA package
- RoHS-compliant 165-ball BGA package available
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2B |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2B |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |