ADI ADSP-SC584CBCZ-4A

The ADSP-SC58x/ADSP-2158x processors belong to the SHARC product family. The ADSP-SC58x processors are based on dual SHARC+ cores and an ARM Cortex-A5 core. The ADSP-SC58x/ADSP-2158x SHARC processors are members of the SIMD SHARC family of DSPs, featuring a Super Harvard architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high-performance audio/floating-point applications, featuring large on-chip SRAM, multiple internal buses that eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI). The latest enhancements to the SHARC+ core include cache improvements, branch prediction, and other instruction set enhancements, while maintaining instruction set compatibility with previous SHARC products. This ARM/SHARC processor integrates numerous industry-leading system peripherals and memory, delivering RISC-style programmability, multimedia support, and advanced signal processing in a single integrated package — making it an ideal platform for next-generation applications. These applications span diverse market segments, from automotive and professional audio to industrial applications requiring high-performance floating-point processing.

• Dual enhanced SHARC+ high-performance floating-point cores, each up to 450 MHz
• Up to 5 Mb (640 kB) L1 SRAM per core with parity support, configurable as cache (optional feature)
• 32-bit, 40-bit, and 64-bit floating-point; 32-bit fixed-point byte, short word, word, and long word addressing
• ARM Cortex-A5 core at 450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle support
• 32 kB L1 instruction cache / 32 kB L1 data cache, 256 kB L2 cache with parity support
• Robust DMA subsystem, memory DMA up to 1.8 GB/s
• On-chip memory protection
• Integrated safety features
• 19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant
• Low system power consumption, automotive temperature range
• Up to 256 kB on-chip L2 SRAM with ECC protection
• On-chip L2 ROM (512 kB)
• Dual L3 interfaces optimized for low system power, providing 16-bit interfaces to DDR3, DDR2, or LPDDR1 SDRAM devices
• Security and protection cryptographic hardware accelerator
• Fast secure boot with IP protection support
• TrustZone support
• High-performance pipelined FFT/IFFT engine
• FIR, IIR, HAE, SINC offload engines
• L1 instruction and data cache units (32/32 kB)
• In-order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set support
• TrustZone security extensions
• Harvard L1 memory system with MMU
• ARM v7 debug architecture
• Trace support via ETM interface
• Extension: VFP unit with no-trap execution (IEEE 754)
• Extension: Media Processing Engine (MPE) with NEON technology
• Extension: Jazelle hardware acceleration

• Automotive
• Professional Audio
• Industrial Applications