ADI AD9286BCPZRL7-500
| Manufacturer | |
| MPN | AD9286BCPZRL7-500 |
| LCSC Part # | C653453 |
| Packaging | LFCSP-48(7x7) |
| Customer # | |
| Key Attributes | LVDS 1.7V~1.9V LFCSP-48(7x7) Analog to Digital Converters (ADC) RoHS |
| Datasheet | ADI AD9286BCPZRL7-500 |
| RoHS Compliance | 1 documents available |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.1LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 60MHz~500MHz | |
| Features | Soft reset | |
| Resolution(Bits) | 500MHz;8 | |
| S/N Ratio | 49.3dB | |
| DNL (LSB) | 0.2LSB | |
| ADC architecture | Pipeline | |
| Programmable Gain | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.1LSB |
| Type | Description | |
|---|---|---|
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 60MHz~500MHz | |
| Features | Soft reset | |
| Resolution(Bits) | 500MHz;8 | |
| S/N Ratio | 49.3dB | |
| DNL (LSB) | 0.2LSB | |
| ADC architecture | Pipeline | |
| Programmable Gain | - |
Introduction
The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance. The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy. The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of -40°C to +85°C.
Features
- Single 1.8 V supply operation
- SNR: 49.3 dBFS at 200 MHz input at 500 MSPS
- SFDR: 65 dBc at 200 MHz input at 500 MSPS
- Low power: 315 mW at 500 MSPS
- On-chip interleaved clocking
- On-chip reference and track-and-hold
- 1.2 V p-p analog input range for each channel
- Differential input with 500 MHz bandwidth
- LVDS-compliant digital output
- On-chip voltage reference and sample-and-hold circuit
- DNL: ±0.2 LSB
- Serial port control options
- Interleaved clock timing adjustment
- Offset binary, Gray code, or twos complement data format
- Optional clock duty cycle stabilizer
- Built-in selectable digital test pattern generation
- Pin-programmable power-down function
- Available in 48-lead LFCSP
Applications
- Battery-powered instruments
- Handheld scope meters
- Low cost digital oscilloscopes
- OTS: video over fiber
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 76.3756 | $ 76.38 |
| 200+ | $ 29.5575 | $ 5911.50 |
| 750+ | $ 28.5187 | $ 21389.03 |
| 1,500+ | $ 28.0048 | $ 42007.20 |
Standard Packaging750/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.1LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 60MHz~500MHz | |
| Features | Soft reset | |
| Resolution(Bits) | 500MHz;8 | |
| S/N Ratio | 49.3dB | |
| DNL (LSB) | 0.2LSB | |
| ADC architecture | Pipeline | |
| Programmable Gain | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | ADI | |
| Packaging | LFCSP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 1.7V~1.9V | |
| Number of Channels | 1 | |
| Integral non - linearity | 0.1LSB |
| Type | Description | |
|---|---|---|
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | 60MHz~500MHz | |
| Features | Soft reset | |
| Resolution(Bits) | 500MHz;8 | |
| S/N Ratio | 49.3dB | |
| DNL (LSB) | 0.2LSB | |
| ADC architecture | Pipeline | |
| Programmable Gain | - |
Introduction
The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance. The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy. The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of -40°C to +85°C.
Features
- Single 1.8 V supply operation
- SNR: 49.3 dBFS at 200 MHz input at 500 MSPS
- SFDR: 65 dBc at 200 MHz input at 500 MSPS
- Low power: 315 mW at 500 MSPS
- On-chip interleaved clocking
- On-chip reference and track-and-hold
- 1.2 V p-p analog input range for each channel
- Differential input with 500 MHz bandwidth
- LVDS-compliant digital output
- On-chip voltage reference and sample-and-hold circuit
- DNL: ±0.2 LSB
- Serial port control options
- Interleaved clock timing adjustment
- Offset binary, Gray code, or twos complement data format
- Optional clock duty cycle stabilizer
- Built-in selectable digital test pattern generation
- Pin-programmable power-down function
- Available in 48-lead LFCSP
Applications
- Battery-powered instruments
- Handheld scope meters
- Low cost digital oscilloscopes
- OTS: video over fiber
C653453 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991C1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991C1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

