RENESAS DA14581-00UNA

The DA14581 integrated circuit is an optimized version of the DA14580, offering a reduced boot time and supporting up to 8 connections. It has a fully integrated radio transceiver and baseband processor for Bluetooth low energy. It can be used as a standalone application processor or as a data pump in hosted systems. The DA14581 supports a flexible memory architecture for storing Bluetooth profiles and custom application code, which can be updated over the air (OTA). The qualified Bluetooth low energy protocol stack and the HCI ready software are stored in a dedicated ROM. All software runs on the ARM Cortex-M0 processor via a simple scheduler. The Bluetooth low energy firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute Protocol (ATT), the Generic Attribute Profile (GATT) and the Generic Access Profile (GAP). All profiles published by the Bluetooth SIG as well as custom profiles are supported. The transceiver interfaces directly to the antenna and is fully compliant with the Bluetooth 4.2 standard. The DA14581 has dedicated hardware for the Link Layer implementation of Bluetooth low energy and interface controllers for enhanced connectivity capabilities.

• Complies with Bluetooth V4.2, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan)
• Supports up to 8 Bluetooth low energy connections
• Fast cold boot in less than 30 ms
• Processing power: 16 MHz 32 bit ARM Cortex-M0 with SWD interface; Dedicated Link Layer Processor
• AES-128 bit encryption Processor
• Memories: 32 kB One-Time-Programmable (OTP) memory; 42 kB System SRAM; 84 kB ROM; 8 kB Retention SRAM
• Integrated Buck/Boost DC-DC converter
• P0, P1 and P2 ports with 3.3 V tolerance
• Easy decoupling of only 4 supply pins
• Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) battery cells
• 10-bit ADC for battery voltage measurement
• General purpose, Capture and Sleep timers
• Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40)
• 2 UARTs with hardware flow control up to 1 MBd
• SPI+ interface
• I2C bus at 100 kHz, 400 kHz
• 3-axes capable Quadrature Decoder
• Analog interfaces: 4-channel 10-bit ADC; Radio transceiver
• Fully integrated 2.4 GHz CMOS transceiver
• Single wire antenna: no RF matching or RX/TX switching required
• Supply current at VBAT3V: TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
• 0 dBm transmit output power
• -20 dBm output power in “Near Field Mode”
• -93 dBm receiver sensitivity