ADI AD9204BCPZ-80

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (-40°C to +85°C).

• 1.8 V analog supply operation
• 1.8 V to 3.3 V output supply
• SNR 61.3 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input
• SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input
• Low power 30 mW per channel at 20 MSPS 63 mW per channel at 80 MSPS
• Differential input with 700 MHz bandwidth
• On-chip voltage reference and sample-and-hold circuit
• DNL δ = ±0.11 LSB
• Serial port control options
• Scalable analog input: 1 V p-p to 2 V p-p differential
• Offset binary, gray code, or twos complement data format
• Optional clock duty cycle stabilizer
• Integer 1-to-8 input clock divider
• Built-in selectable digital test pattern generation
• Energy-saving power-down modes
• Data clock out with programmable clock and data alignment

• Communications
• Diversity radio systems
• Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
• I/Q demodulation systems
• Smart antenna systems
• Battery-powered instruments
• Handheld scope meters
• Ultrasound
• Radar/LIDAR
• PET/SPECT imaging