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MICROCHIP dsPIC33FJ256MC710T-I/PT
| Manufacturer | |
| MPN | dsPIC33FJ256MC710T-I/PT |
| LCSC Part # | C630693 |
| Packaging | TQFP-100(12x12) |
| Customer # | |
| Key Attributes | 160MHz TQFP-100(12x12) Microcontrollers RoHS |
| Datasheet | MICROCHIP dsPIC33FJ256MC710T-I/PT |
| RoHS Compliance | 2 documents available |
| Alternative Parts | 1 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 160MHz |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(12x12) |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 160MHz |
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Features
AI Translation
- Up to 40 MIPS operation (at 3.0 - 3.6V)
- Industrial temperature range (-40°C to +85°C)
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit wide data path
- 24-bit wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly 1 word/1 cycle
- Two 40-bit accumulators
- With rounding and saturation options
- Flexible and powerful addressing modes
- Indirect, Modulo and Bit-Reversed
- Software stack
- 16 × 16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate
- Accumulator write back for DSP operations
- Dual data fetch
- Up to ±16-bit shifts for up to 40-bit data
- 8-channel hardware DMA
- 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA
- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
- Most peripherals support DMA
- 5-cycle latency
- Up to 67 available interrupt sources
- Up to five external interrupts
- Seven programmable priority levels
- Five processor exceptions
- Up to 85 programmable digital I/O pins
- Wake-up/Interrupt-on-Change on up to 24 pins
- Output pins can drive from 3.0V to 3.6V
- All digital input pins are 5V tolerant
- 4 mA sink on all I/O pins
- Flash program memory, up to 256 Kbytes
- Data SRAM, up to 30 Kbytes (includes 2 Kbytes of DMA RAM)
- Flexible clock options
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 24.3437 | $ 24.34 |
| 200+ | $ 9.4214 | $ 1884.28 |
| 500+ | $ 9.0895 | $ 4544.75 |
| 1,200+ | $ 8.9259 | $ 10711.08 |
Standard Packaging1200/Full Reel | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 160MHz |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(12x12) |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 160MHz |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- Up to 40 MIPS operation (at 3.0 - 3.6V)
- Industrial temperature range (-40°C to +85°C)
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit wide data path
- 24-bit wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly 1 word/1 cycle
- Two 40-bit accumulators
- With rounding and saturation options
- Flexible and powerful addressing modes
- Indirect, Modulo and Bit-Reversed
- Software stack
- 16 × 16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate
- Accumulator write back for DSP operations
- Dual data fetch
- Up to ±16-bit shifts for up to 40-bit data
- 8-channel hardware DMA
- 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA
- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
- Most peripherals support DMA
- 5-cycle latency
- Up to 67 available interrupt sources
- Up to five external interrupts
- Seven programmable priority levels
- Five processor exceptions
- Up to 85 programmable digital I/O pins
- Wake-up/Interrupt-on-Change on up to 24 pins
- Output pins can drive from 3.0V to 3.6V
- All digital input pins are 5V tolerant
- 4 mA sink on all I/O pins
- Flash program memory, up to 256 Kbytes
- Data SRAM, up to 30 Kbytes (includes 2 Kbytes of DMA RAM)
- Flexible clock options
C630693 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Alternative Parts
| MPN | Manufacturer | Alternative Type | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|---|
| DSPIC33FJ256MC710-I/PT | MICROCHIP | Direct | TQFP-100(12x12) | 3 | $15.9290 $22.7556 |