MICROCHIP LAN9355TI/ML
| Manufacturer | |
| MPN | LAN9355TI/ML |
| LCSC Part # | C625104 |
| Packaging | QFN-88(12x12) |
| Customer # | |
| Key Attributes | QFN-88(12x12) Controllers RoHS |
| Datasheet | MICROCHIP LAN9355TI/ML |
| RoHS Compliance | 2 documents available |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Controllers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-88(12x12) | |
| Features | Support optical fiber;IEEE1588 timestamp;Cable diagnostics;Power-on reset;Low-power mode |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Controllers | |
| Manufacturer | MICROCHIP |
| Type | Description | |
|---|---|---|
| Packaging | QFN-88(12x12) | |
| Features | Support optical fiber;IEEE1588 timestamp;Cable diagnostics;Power-on reset;Low-power mode |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- High performance 3-port switch with VLAN, QoS packet prioritization, rate limiting, IGMP monitoring and management functions
- Interfaces at up to 200Mbps via Turbo MII
- Integrated Ethernet PHYs with HP Auto-MDIX
- Compliant with Energy Efficient Ethernet 802.3az
- Wake on LAN (WoL) support
- Integrated IEEE 1588v2 hardware time stamp unit
- Cable diagnostic support
- 1.8V to 3.3V variable voltage I/O
- Integrated 1.2V regulator for single 3.3V operation
- Ethernet Switch Fabric: 32K buffer RAM, 512 entry forwarding table
- Port based IEEE 802.1Q VLAN support (16 groups)
- Programmable IEEE 802.1Q tag insertion/removal
- IEEE 802.1D spanning tree protocol support
- 4 separate transmit queues available per port
- Fixed or weighted egress priority servicing
- QoS/CoS Packet prioritization
- Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value
- Programmable Traffic Class map based on input priority on per port basis
- Remapping of 802.1Q priority field on per port basis
- Programmable rate limiting at the ingress with coloring and random early discard, per port / priority
- Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority
- IGMP v1/v2/v3 monitoring for Multicast packet filtering
- Programmable broadcast storm protection with global % control and enable per port
- Programmable buffer usage limits
- Dynamic queues on internal memory
- Programmable filter by MAC address
- Switch Management: Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair
- Fully compliant statistics (MIB) gathering counters
- Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC modes
- Port 1: Internal PHY, MII MAC, MII PHY, RMII MAC, RMII PHY modes
- Port 2: Internal PHY
- 2 internal 10/100 PHYs with HP Auto-MDIX support
- 200Mbps Turbo MII (PHY or MAC mode)
- Fully compliant with IEEE 802.3 standards
- 10BASE-T and 100BASE-TX support
- 100BASE-FX support via external fiber transceiver
- Full and half duplex support, full duplex flow control
- Backpressure (forced collision) half duplex flow control
- Automatic flow control based on programmable levels
- Automatic 32-bit CRC generation and checking
- Programmable interframe gap, flow control pause value
- Auto-negotiation, polarity correction & MDI/MDI-X
- IEEE 1588v2 hardware time stamp unit: Global 64-bit tunable clock
- Boundary clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay
- Transparent Clock with Ordinary Clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay
- Fully programmable timestamp on TX or RX, timestamp on GPIO
- 64-bit timer comparator event generation (GPIO or IRQ)
- Comprehensive power management features: 3 power-down levels
- Wake on link status change (energy detect)
- Magic packet wakeup, Wake on LAN (WoL), wake on broadcast, wake on perfect DA
- Wakeup indicator event signal
- Power and I/O: Integrated power-on reset circuit
- Latch-up performance exceeds 150mA per EIA/JESD78, Class II
- JEDEC Class 3A ESD performance
- Single 3.3V power supply (integrated 1.2V regulator)
- Additional Features: Multifunction GPIOs
- Ability to use low cost 25MHz crystal for reduced BOM
- Packaging: Pb-free RoHS compliant 88-pin QFN or 80-pin TQFPEP
- Available in commercial and industrial temp. ranges
Applications
AI Translation
- Cable, satellite, and IP set-top boxes
- Digital televisions & video recorders
- VoIP/Video phone systems, home gateways
- Test/Measurement equipment, industrial automation
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Controllers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-88(12x12) | |
| Features | Support optical fiber;IEEE1588 timestamp;Cable diagnostics;Power-on reset;Low-power mode |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Controllers | |
| Manufacturer | MICROCHIP |
| Type | Description | |
|---|---|---|
| Packaging | QFN-88(12x12) | |
| Features | Support optical fiber;IEEE1588 timestamp;Cable diagnostics;Power-on reset;Low-power mode |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- High performance 3-port switch with VLAN, QoS packet prioritization, rate limiting, IGMP monitoring and management functions
- Interfaces at up to 200Mbps via Turbo MII
- Integrated Ethernet PHYs with HP Auto-MDIX
- Compliant with Energy Efficient Ethernet 802.3az
- Wake on LAN (WoL) support
- Integrated IEEE 1588v2 hardware time stamp unit
- Cable diagnostic support
- 1.8V to 3.3V variable voltage I/O
- Integrated 1.2V regulator for single 3.3V operation
- Ethernet Switch Fabric: 32K buffer RAM, 512 entry forwarding table
- Port based IEEE 802.1Q VLAN support (16 groups)
- Programmable IEEE 802.1Q tag insertion/removal
- IEEE 802.1D spanning tree protocol support
- 4 separate transmit queues available per port
- Fixed or weighted egress priority servicing
- QoS/CoS Packet prioritization
- Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value
- Programmable Traffic Class map based on input priority on per port basis
- Remapping of 802.1Q priority field on per port basis
- Programmable rate limiting at the ingress with coloring and random early discard, per port / priority
- Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority
- IGMP v1/v2/v3 monitoring for Multicast packet filtering
- Programmable broadcast storm protection with global % control and enable per port
- Programmable buffer usage limits
- Dynamic queues on internal memory
- Programmable filter by MAC address
- Switch Management: Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair
- Fully compliant statistics (MIB) gathering counters
- Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC modes
- Port 1: Internal PHY, MII MAC, MII PHY, RMII MAC, RMII PHY modes
- Port 2: Internal PHY
- 2 internal 10/100 PHYs with HP Auto-MDIX support
- 200Mbps Turbo MII (PHY or MAC mode)
- Fully compliant with IEEE 802.3 standards
- 10BASE-T and 100BASE-TX support
- 100BASE-FX support via external fiber transceiver
- Full and half duplex support, full duplex flow control
- Backpressure (forced collision) half duplex flow control
- Automatic flow control based on programmable levels
- Automatic 32-bit CRC generation and checking
- Programmable interframe gap, flow control pause value
- Auto-negotiation, polarity correction & MDI/MDI-X
- IEEE 1588v2 hardware time stamp unit: Global 64-bit tunable clock
- Boundary clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay
- Transparent Clock with Ordinary Clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay
- Fully programmable timestamp on TX or RX, timestamp on GPIO
- 64-bit timer comparator event generation (GPIO or IRQ)
- Comprehensive power management features: 3 power-down levels
- Wake on link status change (energy detect)
- Magic packet wakeup, Wake on LAN (WoL), wake on broadcast, wake on perfect DA
- Wakeup indicator event signal
- Power and I/O: Integrated power-on reset circuit
- Latch-up performance exceeds 150mA per EIA/JESD78, Class II
- JEDEC Class 3A ESD performance
- Single 3.3V power supply (integrated 1.2V regulator)
- Additional Features: Multifunction GPIOs
- Ability to use low cost 25MHz crystal for reduced BOM
- Packaging: Pb-free RoHS compliant 88-pin QFN or 80-pin TQFPEP
- Available in commercial and industrial temp. ranges
Applications
AI Translation
- Cable, satellite, and IP set-top boxes
- Digital televisions & video recorders
- VoIP/Video phone systems, home gateways
- Test/Measurement equipment, industrial automation
C625104 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

