Winbond W74M12JWSSIQ

The W74M12JW (128Mb) serial flash provides a storage solution for systems with limited space, pin count, and power consumption. The W74M series offers flexibility and performance far exceeding that of ordinary serial flash devices. They are well-suited for loading code from flash to RAM, executing code directly from Dual/Quad SPI, and storing voice, text, and data. The device operates from a single 1.7V to 1.95V supply with low current consumption. All devices are available in space-saving packages.

The W74M12JW supports Standard SPI, Dual/Quad I/O SPI, and a 2-clock instruction cycle Quad Peripheral Interface: Serial Clock, Chip Select, Serial Data I/O0, I/O1, I/O2, and I/O3. SPI clock frequencies up to 104MHz are supported, with equivalent clock rates of 208MHz (104MHz×2) for Dual I/O and 416MHz (104MHz×4) for Quad I/O when using Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can surpass standard asynchronous 8-bit and 16-bit parallel flash. Continuous Read mode enables efficient memory access with only 8-clock instruction overhead to read a 24-bit address, enabling true Execute-in-Place (XIP) operation. The device supports JEDEC standard Manufacturer and Device ID, Serial Flash Discoverable Parameters (SFDP) registers, a 64-bit serial number, and three 256-byte security registers.

The W74M product line integrates a standard HMAC SHA-256 cryptographic accelerator for key establishment between devices or systems to enable secure authentication. Secure authentication is accomplished using a root key along with session-based HMAC keys secretly shared between the host and flash memory.

Each W74M device is equipped with four sets of non-volatile 256-bit root key storage; four sets of volatile 256-bit HMAC key storage; and four sets of non-volatile 32-bit monotonic counter value storage. These four sets allow one device to be paired with up to four different hosts. A host can be another device (such as a microprocessor) or a system.

Each monotonic counter paired with a host shares a counter value that can be incremented. The host determines the nonce and increment rate during initial pairing. The continuously changing counter value serves as a method to prevent device counterfeiting and replay attacks.

• New serial Flash series, 128Mb/16MB capacity
• Standard SPI, Dual SPI, and Quad SPI interface support
• Software reset support
• 104MHz single/dual/quad SPI clock support, equivalent dual/quad SPI rate up to 208/416MHz
• Continuous data transfer rate up to 50MB/s
• Minimum 100,000 erase/program cycles
• Data retention exceeding 20 years
• Single supply voltage range 1.7V to 1.95V
• Operating current 1mA, typical power-down current less than 1μA
• Operating temperature range -40°C to +85°C
• Flexible architecture with 4KB sectors, uniform sector/block erase support
• 1 to 256 bytes programmable per page
• Erase/program suspend and resume operation support
• Integrated HMAC-SHA-256 engine
• 4 monotonic Flash counter support
• 64-bit ID per device
• Software write protection support
• Power-up lock and OTP protection support
• Top/bottom and complementary array protection support
• Individual block/sector array protection support
• SFDP register support
• 3 × 256-byte security registers with OTP lock
• Volatile and non-volatile status register support