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SILICON LABS EM250-RT

Manufacturer
MPN
EM250-RT
LCSC Part #
C5729364
Packaging
QFN-48(7x7)
Customer #
Key Attributes
-100dBm 250Kbps 2.4GHz~2.5GHz 2.4GHz 2.1V~3.6V QFN-48(7x7) RF Transceiver ICs
DatasheetSILICON LABS EM250-RT
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryRF and Wireless/RF Transceiver ICs
ManufacturerSILICON LABS
PackagingQFN-48(7x7)
Sensitivity-100dBm
Data Rate250Kbps
Applications802.15.4;ZigBee
Frequency Range2.4GHz~2.5GHz
Typical Application Frequency2.4GHz
Output Power5dBm
Receive Current36mA
Interface TypeADC;GPIO;I2C;SPI;UART
Operating Temperature-40℃~+85℃
Voltage - Supply2.1V~3.6V
Typetransceiver
Current Of Transmitting36mA
FeaturesAutomatic response function;Supports RSSI function;Power-on Reset;CRC check function;DMA function;Supports software reset

Introduction

AI Translation

The EM250 is a single-chip solution that integrates a 2.46Hz, IEEE 802.15.4-compliant transceiver with a 16-bit XAP2b microprocessor. It contains integrated Flash and RAM memory and peripherals of use to designers of ZigBee-based applications. The transceiver utilizes an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE 802.15.4-2003 standard by over 15dB. The integrated receive channel filtering allows for co-existence with other communication standards in the 2.4GHz spectrum such as IEEE 802.11g and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count low. An optional high performance radio mode (boost mode) is software selectable to boost dynamic range by a further 3dB. The XAP2b microprocessor is a power-optimized core integrated in the EM250. It supports two different modes of operation—System Mode and Application Mode. The EmberZNet PRO stack runs in System Mode with full access to all areas of the chip. Application code runs in Application Mode with limited access to the EM250 resources; this allows for the scheduling of events by the application developer while preventing modification of restricted areas of memory and registers. This architecture results in increased stability and reliability of deployed solutions. The EM250 has 128kB of embedded Flash memory and 5kB of integrated RAM for data and program storage. The EM250 software stack employs an effective wear-leveling algorithm in order to optimize the lifetime of the embedded Flash. To maintain the strict timing requirements imposed by ZigBee and the IEEE 802.15.4-2003 standard, the EM250 integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. In addition, the EM250 allows for true MAC level debugging by integrating the Packet Trace Interface. To support user-defined applications, a number of peripherals such as GPIO, UART, SPI, I²C, ADC, and general-purpose timers are integrated. Also, an integrated voltage regulator, power-on-reset circuitry, sleep timer, and low-power sleep modes are available. The deep sleep mode draws less than 1μA, allowing products to achieve long battery life. Finally, the EM250 utilizes the non-intrusive SIF module for powerful software debugging and programming of the XAP2b microcontroller.

Features

AI Translation
  • Robust RX filtering allows co-existence with IEEE 802.11g and Bluetooth devices
    • 99dBm RX sensitivity (1% PER, 20byte packet)
    • 3dBm nominal output power
  • Increased radio performance mode (boost mode) gives - 100dBm sensitivity and + 5dBm transmit power
  • Integrated VCO and loop filter
  • Integrated IEEE 802.15.4 PHY and lower MAC with DMA
  • Integrated hardware support for Packet Trace Interface for the Ember development environment
  • Provides integrated RC oscillator for low power operation
  • Supports optional 32.768kHz crystal oscillator for higher accuracy needs
  • 16-bit XAP2b microprocessor
  • Integrated memory: 128kB of Flash, 5kB of SRAM
  • Configurable memory protection scheme
  • Two sleep modes: Processor idle, Deep sleep—1.0μμ (1.5μA with optional 32.768kHz oscillator enabled)
  • Seventeen GPIO pins with alternate functions
  • Two Serial Controllers with DMA: SC1: I²C master, SPI master + UART; SC2: I²C master, SPI master/slave
  • Two 16-bit general-purpose timers; one 16-bit sleep timer
  • Watchdog timer and power-on-reset circuitry
  • Non-intrusive debug interface (SIF)
  • Integrated AES encryption accelerator
  • Integrated ADC module first-order, sigmadelta converter with 12-bit resolution
  • Integrated 1.8V voltage regulator

Applications

AI Translation
  • Building automation and control
  • Home automation and control
  • Home entertainment control
  • Asset tracking