GSI Technology GS81313LQ18GK-800I

SigmaQuad-IIIe ECCRAM is one half of the independent I/O in the high-performance ECCRAM family SigmaQuad-IIIe/SigmaDDR-IIIe. While very similar to GSI's second-generation network SRAM (SigmaQuad-II/SigmaDDR-II series), these third-generation devices offer several new features that help significantly improve performance. GSI's ECCRAM implements an ECC algorithm that detects and corrects all single-bit memory errors, including those caused by SER events such as cosmic rays, alpha particles, etc. The soft error rate of these devices is expected to be <0.002 FITs/Mb, representing a 5-order-of-magnitude improvement over comparable SRAMs without on-chip ECC, which typically exhibit SERs of 200 FITs/Mb or higher. All cited SER values are at sea level in New York City.

• 4Mb x 36 and 8Mb x 18 organization
• Operating frequency 800 MHz
• Transaction rate 1.6 BT/s (billion transactions per second)
• Data bandwidth 115 Gb/s (in x36 devices)
• Independent I/O DDR data bus
• Non-multiplexed DDR address bus
• Two operations per clock cycle — read and write
• Burst length 2 read and write operations
• 3-cycle read latency
• On-chip ECC, near-zero soft error rate
• Core voltage 1.25V ~ 1.3V
• HSTL I/O interface voltage 1.2V ~ 1.3V
• Configurable ODT (On-Die Termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant boundary scan
• 260-pin, 14mm × 22mm, 1mm ball pitch, 6/6 RoHS-compliant BGA package