ADI AD9083BBCZ

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the Σ-Δ ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications. Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, TRIG±, and SYNCINB± input pins. The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI).

• 1.0 V and 1.8 V supply operation
• 125 MHz usable analog input bandwidth
• Sample rate up to 2 GSPS
• Noise spectral density in 100 MHz bandwidth = −145 dBFS/Hz, 2.0 GSPS encode
• SNR = 66 dBFS in 100 MHz bandwidth, 2.0 GSPS encode
• SNR = 82 dBFS in 15.625 MHz bandwidth, 2.0 GSPS encode
• SFDR = ±80 dBc in 100 MHz bandwidth, 2.0 GSPS encode
• SFDR = 80 dBc in 15.625 MHz bandwidth, 2.0 GSPS encode
• 90 mW total power per channel at 2.0 GSPS (default settings)
• Flexible input range: 0.5 V p-p to 2 V p-p differential
• 90 dB channel crosstalk, 2.0 GSPS encode
• Digital processor CIC decimation filter Programmable DDC Data gating
• JESD204B Subclass 1 encoded outputs Supports up to 16 Gbps/lane Flexible sample data processing Flexible JESD204B lane configurations
• Large signal dither
• Serial port control

• Millimeter wave imaging
• Electronic beam forming and phased arrays
• Multichannel wideband receivers
• Electronic support measures