RENESAS 71V35761SA166BQI

The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, address, and control registers. Internal logic allows the SRAM to generate self-timed writes based on decisions that can be deferred until the end of the write cycle. An internal burst address counter accepts the first-cycle address from the processor to initiate an access sequence. The first-cycle output data is pipelined one cycle and becomes available on the next rising clock edge. If burst mode operation is selected (ADV=Low), the output data for the subsequent three cycles will be available to the user on the next three rising clock edges. The sequence of these three addresses is defined by the internal burst counter and the LBO input pin. The IDT71V35761/781 SRAMs are fabricated using a high-performance CMOS process and are packaged in JEDEC standard 14mm x 20mm 100-pin Thin Plastic Quad Flat Pack (TQFP), as well as 119-ball BGA and 165-ball Fine-Pitch BGA packages.

• 128K x 36, 256K x 18 memory configurations
• High system speed support: Commercial: 200MHz 3.1ns clock access time; Commercial and Industrial: 183MHz 3.3ns clock access time, 166MHz 3.5ns clock access time
• LBO input selectable interleaved or linear burst mode
• Self-timed write cycle with Global Write (GW), Byte Write Enable (BWE), and Byte Write (BWx)
• 3.3V core supply
• Power-down control via ZZ input
• 3.3V I/O
• Optional boundary scan JTAG interface (IEEE 1149.1 compliant)
• Available in JEDEC standard 100-pin plastic Thin Quad Flat Pack (TQFP), 119-ball BGA, and 165-ball Fine Pitch BGA packages