LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Nexperia 74LVTH125BQ,115 product image
Images for reference only

Nexperia 74LVTH125BQ,115

Manufacturer
MPN
74LVTH125BQ,115
LCSC Part #
C549065
Packaging
DHVQFN-14-EP(2.5x3)
Customer #
Key Attributes
2.7V~3.6V 1 3 2.7ns@3.3V,50pF DHVQFN-14-EP(2.5x3) Buffers, Drivers, Receivers, Transceivers RoHS
DatasheetNexperia 74LVTH125BQ,115
RoHS Compliance2 documents available
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerNexperia
PackagingDHVQFN-14-EP(2.5x3)
Input type-
Voltage - Supply2.7V~3.6V
Output TypeTri-State
Operating Temperature-40℃~+85℃
Quiescent Supply Current190uA
FunctionOutput enable;Bus hold;Power-off isolation;Hot-swap support
Current - Output High(IOH)32mA
Series74LVTH
Current - Output Low(IOL)64mA
Number of Bits per Element1
Channel TypeUnidirectional
Number of Elements3
Propagation Delay2.7ns@3.3V,50pF

Introduction

AI Translation

The 74LVT125; 74LVTH125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features

AI Translation
  • Quad bus interface
  • 3-state buffers
  • Wide supply voltage range from 2.7 to 3.6 V
  • BiCMOS high speed and output drive
  • Output capability: +64 mA and -32 mA
  • Direct interface with TTL levels
  • Overvoltage tolerant inputs to 5.5 V
  • Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
  • Live insertion and extraction permitted
  • No bus current loading when output is tied to 5 V bus
  • Power-up 3-state
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
  • Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to 85 °C

Applications

AI Translation
  • Bus interface
  • 3-state buffer
  • Data input hold
  • Partial power-down applications
  • High-speed and output drive
  • Direct TTL-level interface
  • Overvoltage-tolerant inputs
  • Hot insertion and extraction
  • No bus current loading
  • Power-up 3-state
  • Partial power-down mode operation