Nexperia 74LV393D,118

Manufacturer	Nexperia
MPN	74LV393D,118
LCSC Part #	C547971
Packaging	SO-14
Customer #
Key Attributes	Falling Edge 2 20MHz SO-14 Counters, Dividers RoHS
Datasheet	Nexperia 74LV393D,118
RoHS Compliance	2 documents available
Alternative Parts	5

Products Specifications

All

Type	Description
Category	Integrated Circuits (ICs)/Logic/Counters, Dividers
Manufacturer	Nexperia
Packaging	SO-14
Logic Family	74LV
Voltage - Supply	1V~3.6V
Direction	Up Counter
Trigger Type	Falling Edge
Timing	Asynchronous
Operating Temperature	-40℃~+125℃
Reset	Asynchronous
Number of Elements	2
Propagation Delay	14ns@3.6V,50pF
Count Rate	20MHz
Features	Programmable divide ratio;Reset function

AI Translation

Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
Typical V_OLP (output ground bounce) 0.8 V at V_CC = 3.3 V, T_amb = 25 ℃
Typical V_OHV (output V_OH undershoot) 2 V at V_CC = 3.3 V, T_amb = 25 ℃
Two 4-bit binary counters with individual clocks
Divide-by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
Complies with JEDEC standard no. 7A
ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

AI Translation

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100% Authentic · 30-Day Return or Replacement

All

Type	Description
Category	Integrated Circuits (ICs)/Logic/Counters, Dividers
Manufacturer	Nexperia
Packaging	SO-14
Logic Family	74LV
Voltage - Supply	1V~3.6V
Direction	Up Counter
Trigger Type	Falling Edge
Timing	Asynchronous
Operating Temperature	-40℃~+125℃
Reset	Asynchronous
Number of Elements	2
Propagation Delay	14ns@3.6V,50pF
Count Rate	20MHz
Features	Programmable divide ratio;Reset function

AI Translation

Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
Typical V_OLP (output ground bounce) 0.8 V at V_CC = 3.3 V, T_amb = 25 ℃
Typical V_OHV (output V_OH undershoot) 2 V at V_CC = 3.3 V, T_amb = 25 ℃
Two 4-bit binary counters with individual clocks
Divide-by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
Complies with JEDEC standard no. 7A
ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

AI Translation