TI LMK04828BISQ/NOPB

The LMK0482x family is the highest performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK0482x family ideal for providing flexible high performance clocking trees.

• JEDEC JESD204B Support
• Ultra-Low RMS Jitter
• 88 fs RMS Jitter (12 kHz to 20 MHz)
• 91 fs RMS Jitter (100 Hz to 20 MHz)
• –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
• Up to 7 SYSREF Clocks
• Maximum Clock Output Frequency 3.1 GHz
• LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
• Dual Loop PLLatinum™ PLL Architecture
• Up to 3 Redundant Input Clocks – Automatic and Manual Switch-Over Modes
• Hitless Switching and LOS
• Integrated Low-Noise Crystal Oscillator Circuit
• Holdover mode when Input Clocks are Lost

• Wireless Infrastructure
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Medical / Video / Test and Measurement