ST STM32N657I0H3Q

This device integrates a high-performance Arm Cortex-M55 processor, ST Neural-ART neural network accelerator, H.264 video encoder, Neo-Chrom 2.5D GPU, and large-capacity contiguous SRAM. It features an advanced 32-bit Arm Cortex-M55 core running at up to 800 MHz, with support for Arm M-Profile Vector Extension and Helium technology, along with single-precision and half-precision floating-point units. The dedicated ST Neural-ART accelerator operates at up to 1 GHz, optimized for deep neural network inference, supporting real-time encryption/decryption and on-the-fly weight decompression. The device provides 4.2 Mbyte of contiguous SRAM and TCM memory with ECC, along with a flexible external memory controller and XSPI interface. The graphics subsystem includes a Neo-Chrom 2.5D GPU and Chrom-ART accelerator, with hardware JPEG codec and LCD-TFT controller support. The video subsystem features parallel and MIPI CSI-2 camera interfaces, an image signal processor, and H.264 video encoding acceleration supporting multiple profiles. Security features include Arm TrustZone, SESIP Level 3 certification, secure boot, dual AES coprocessors, a public key accelerator, and a true random number generator. Communication peripherals include USB 2.0 OTG, Ethernet, I2C, I3C, SPI, SAI, USART, UART, SDMMC, and FDCAN. Low-power modes include Sleep, Stop, and Standby. The device also integrates a rich set of analog peripherals, timers, watchdogs, debug interfaces, and general-purpose I/Os, available in multiple ECOPACK2-compliant packages.

• Incorporates ST's advanced proprietary technology
• Arm 32-bit Cortex-M55 core, 3360 CoreMark, up to 800 MHz, 1280 DMIPS, 32-Kbyte instruction cache, 32-Kbyte data cache
• Arm M-Profile Vector Extension
• Arm Helium technology
• Arm TrustZone memory protection unit, nested vectored interrupt controller
• Single-precision and half-precision FPU
• ST Neural-ART Accelerator, up to 1 GHz, 600 Gops, 288 MAC/cycle
• Dedicated hardware unit for deep neural network inference
• Flexible dedicated streaming processing engine
• Real-time encryption/decryption
• On-the-fly weight decompression
• 4.2 Mbyte contiguous SRAM
• 128-Kbyte ECC-protected tightly coupled memory RAM (for critical real-time data) + 64-Kbyte ECC-protected instruction tightly coupled memory RAM (for critical real-time routines)
• 8-Kbyte backup SRAM available in VBAT mode
• Flexible external memory controller with cryptographic engine, up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND flash
• XSPI supporting serial PSRAM, NAND, NOR, HyperRAM/HyperFlash frame formats
• 2 ports: XSPIM 8-bit and 16-bit configuration, up to 200 MHz
• Neo-Chrom 2.5D GPU: scaling, rotation, alpha blending, texture mapping, perspective transformation
• Chrom-ART Accelerator
• Hardware JPEG codec with MJPEG support
• LCD-TFT controller supporting up to XGA resolution
• Parallel and 2-lane MIPI CSI-2 camera interface
• Image signal processor with three parallel processing pipelines on the same input stream: bad pixel correction, decimation, black level, exposure, demosaicing, column conversion, contrast, cropping, downscaling, region of interest, gamma correction, YUV conversion, pixel packing
• H.264 video encoding acceleration: Baseline Profile, Main Profile, High Profile, Level 1 to 5.2, supports 1080p30 and 720p60
• Arm TrustZone with securable I/Os, memories, and peripherals
• SESIP Level 3 certified, Arm PSA certified
• Flexible lifecycle scheme with read-out protection and password-protected debug
• Secure customer key provisioning in OTP fuses
• Secure boot code in ROM for decryption and verification of customer update root of trust
• Secure data storage using hardware keys
• Secure firmware upgrade support using Trusted Firmware-M
• Two AES coprocessors, one with DPA resistance
• Public-key accelerator with DPA resistance
• On-the-fly encryption/decryption of external memories
• Hash hardware accelerator
• NIST SP800-90B compliant true random number generator
• 96-bit unique ID
• 1.5-Kbyte OTP fuses
• Active tamper detection
• 2× USB 2.0 High-Speed/Full-Speed device/host OTG controllers (one with UCPD USB Type-C power delivery)
• 10 Mbit, 100 Mbit, and 1 Gbit Ethernet with Time-Sensitive Networking support
• 4× I2C Fm+ interfaces + 2× I3C interfaces
• 6× SPI, 4 of which support I2S
• 2× SAI supporting four digital microphones
• 5× USART, 5× UART + 1× LPUART
• 2× SDMMC controllers
• 3× FDCAN with TTCAN support
• Sleep, Stop, and Standby modes
• VBAT supply for RTC, 32× 32-bit backup registers, and 8-Kbyte backup SRAM
• 1× high-resolution timer
• 4× 32-bit timers with up to four input capture/output compare/PWM or pulse counter channels and quadrature encoder input
• 2× 16-bit advanced motor control timers
• 13× 16-bit general-purpose timers and 5× 16-bit low-power timers
• 2× watchdogs
• 1× SysTick timer
• RTC with sub-second accuracy and hardware calendar
• Development support: Serial Wire Debug, JTAG
• Embedded Trace Macrocell
• Up to 165 I/O pins
• 1× temperature sensor
• 2× ADC, up to 12-bit resolution, up to 5 Msps, up to 20 channels
• 1× analog data filter with summing-difference function, 1× multi-data filter
• POR, PDR, programmable BOR, and BRR
• Embedded SMPS buck converter supplying VDDCORE
• 1.71 to 3.6 V application supply and I/Os
• Dedicated supply for USB and XSPI I/Os
• Backup regulator
• Analog peripheral voltage reference
• Internal oscillators: 64 MHz HSI, 4 MHz MSI, 32 kHz LSI
• External oscillators: 16 to 48 MHz HSE, 32.768 kHz LSE
• 4× PLLs

• Industrial Automation
• Consumer Electronics
• Medical Devices
• Smart Home
• Automotive Electronics