TI JM38510/30107B2A

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.

• '174, LS174, S174 contain 6 flip-flops with single-ended outputs
• '175, LS175, S175 contain 4 flip-flops with complementary outputs
• Three performance ranges available
• Buffered clock input and direct clear input
• Individual data input per flip-flop
• Available in J, W, N, D, FK package types
• '174, '175 typical clock frequency 35MHz, typical power dissipation 38mW per flip-flop
• LS174, LS175 typical clock frequency 40MHz, typical power dissipation 14mW per flip-flop
• S174, S175 typical clock frequency 110MHz, typical power dissipation 75mW per flip-flop
• SN54174, SN54175, SN74174, SN74175 clock and D input equivalent resistance nominal value 8kΩ, clear input equivalent resistance nominal value 4kΩ
• SN54LS174, SN54LS175, SN74LS174, SN74LS175 clock input equivalent resistance nominal value 23kΩ, clear and D input equivalent resistance nominal value 28kΩ
• Maximum ratings: supply voltage VCC 7V, input voltage 5.5V
• SN54 series devices operating free-air temperature range -55℃ to 125℃, SN74 series devices operating free-air temperature range 0℃ to 70℃, storage temperature range -65℃ to 150℃

• Buffer/Storage Registers
• Shift Registers
• Pattern Generators