TI JM38510/07102BEA

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock puise. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

• Fully buffered design for isolation from external interference
• Multiple package options available, including small outline plastic, ceramic chip carrier, flat pack, plastic DIP, and ceramic DIP
• Available packages: J, W, D, N, and FK packages
• Preset and clear inputs independently control output state, unaffected by other inputs
• Clock triggering independent of clock pulse rise time
• Input data changes after hold time do not affect output state
• Configurable for use as a toggle flip-flop
• SN54LS112A and SN54S112 operating temperature range: -55℃ to 125℃; SN74LS112A and SN74S112A operating temperature range: 0℃ to 70℃
• Maximum ratings: supply voltage VCC = 7V; 'LS112A input voltage = 7V; SN54LS112 and SN74LS112A input voltage = 5.5V; storage temperature range: -65℃ to 150℃
• Logic symbols compliant with ANSI/IEEE Std 91-1984 and IEC Publication 617-12
• Available in RoHS-compliant and low-halogen versions meeting EU requirements