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TI CDCDB800RSLR
| Manufacturer | |
| MPN | CDCDB800RSLR |
| LCSC Part # | C3613711 |
| Packaging | VQFN-48(6x6) |
| Customer # | |
| Key Attributes | 3V~3.6V 250MHz 8 VQFN-48(6x6) Clock Buffers, Drivers |
| Datasheet | TI CDCDB800RSLR |
| Alternative Parts | 3 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | TI | |
| Packaging | VQFN-48(6x6) | |
| Operating Temperature | -40℃~+105℃ | |
| Voltage - Supply | 3V~3.6V | |
| Features | Multi-channel fan-out/isolation drive;Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 1 | |
| Output Frequency(Max) | 250MHz | |
| Number of outputs | 8 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | TI | |
| Packaging | VQFN-48(6x6) | |
| Operating Temperature | -40℃~+105℃ | |
| Voltage - Supply | 3V~3.6V |
| Type | Description | |
|---|---|---|
| Features | Multi-channel fan-out/isolation drive;Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 1 | |
| Output Frequency(Max) | 250MHz | |
| Number of outputs | 8 |
Introduction
CDCDB800 is an 8-output LP-HCSL clock buffer compliant with the DB800ZL standard, capable of distributing reference clocks for PCIe Gen 1 through Gen 6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. All 8 outputs can be individually configured and controlled via the SMBus interface and 8 output enable pins. The CDCDB800 is a DB800ZL-derivative buffer that meets or exceeds the system parameter specifications defined in DB800ZL. It also meets or exceeds the parameter specifications of DB2000Q. The CDCDB800 is available in a 6mm × 6mm 48-pin VQFN package.
Features
- 8 LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output termination
- 8 hardware output enable (OE#) controls
- Additive phase jitter after Gen 6 PCIE filter: 20fs RMS (max)
- Additive phase jitter after Gen 5 PCIE filter: 25fs RMS (max)
- Additive phase jitter after DB2000Q filter: 38fs RMS (max)
- Supports Common Clock (CC) and Independent Reference (IR) architectures
- Spread spectrum compatible
- Output-to-output skew: < 50ps
- Input-to-output delay: < 3ns
- Fail-safe inputs
- Programmable output slew rate control
- 3.3V core and IO supply voltage
- Hardware-controlled power-down mode (PD#)
- Current consumption: 72mA (max)
- 6mm × 6mm 48-pin VQFN package
Applications
- Micro servers and tower servers
- Storage area network and host bus adapter cards
- Network-attached storage
- Hardware accelerators
- Rack servers
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | TI | |
| Packaging | VQFN-48(6x6) | |
| Operating Temperature | -40℃~+105℃ | |
| Voltage - Supply | 3V~3.6V | |
| Features | Multi-channel fan-out/isolation drive;Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 1 | |
| Output Frequency(Max) | 250MHz | |
| Number of outputs | 8 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | TI | |
| Packaging | VQFN-48(6x6) | |
| Operating Temperature | -40℃~+105℃ | |
| Voltage - Supply | 3V~3.6V |
| Type | Description | |
|---|---|---|
| Features | Multi-channel fan-out/isolation drive;Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 1 | |
| Output Frequency(Max) | 250MHz | |
| Number of outputs | 8 |
Introduction
CDCDB800 is an 8-output LP-HCSL clock buffer compliant with the DB800ZL standard, capable of distributing reference clocks for PCIe Gen 1 through Gen 6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. All 8 outputs can be individually configured and controlled via the SMBus interface and 8 output enable pins. The CDCDB800 is a DB800ZL-derivative buffer that meets or exceeds the system parameter specifications defined in DB800ZL. It also meets or exceeds the parameter specifications of DB2000Q. The CDCDB800 is available in a 6mm × 6mm 48-pin VQFN package.
Features
- 8 LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output termination
- 8 hardware output enable (OE#) controls
- Additive phase jitter after Gen 6 PCIE filter: 20fs RMS (max)
- Additive phase jitter after Gen 5 PCIE filter: 25fs RMS (max)
- Additive phase jitter after DB2000Q filter: 38fs RMS (max)
- Supports Common Clock (CC) and Independent Reference (IR) architectures
- Spread spectrum compatible
- Output-to-output skew: < 50ps
- Input-to-output delay: < 3ns
- Fail-safe inputs
- Programmable output slew rate control
- 3.3V core and IO supply voltage
- Hardware-controlled power-down mode (PD#)
- Current consumption: 72mA (max)
- 6mm × 6mm 48-pin VQFN package
Applications
- Micro servers and tower servers
- Storage area network and host bus adapter cards
- Network-attached storage
- Hardware accelerators
- Rack servers
C3613711 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |