Rochester Electronics MD82C284-10/B

The 82C284 generates the clock, ready, and reset signals required for the 80286 processor and support components. It incorporates a crystal-controlled oscillator, clock generator, peripheral clock generator, multi-bus ready synchronization logic, and system reset generation logic. The CLK output provides fundamental timing control for 80286 systems; its output characteristics are sufficient to drive MOS devices and can be generated by either an internal crystal oscillator or an external source. PCLK is a divide-by-2 output of CLK with a 50% duty cycle, features MOS output drive characteristics, and is typically synchronized with the internal processor clock. The oscillator circuit is a linear Pierce oscillator requiring an external parallel-resonant, fundamental-mode crystal; the crystal frequency should be twice the desired internal processor clock frequency. Due to the very fast rise and fall times of the CLK output, proper termination of the CLK line is recommended at frequencies above 10MHz to prevent signal reflections and ringing. The reset logic provides a RESET output to bring the system into a known initial state.

• High-speed CHMOS III technology
• System reset output generation
• Available in 18-pin Cerclip and 20-pin PLCC packages

• 80286 processor systems