Intel/Altera EPF10K100ABI356-2N

Industry's first embedded PLD. Based on reconfigurable CMOS SRAM cells, the FLEX architecture integrates all the features required to implement common gate array macrofunctions. FLEX 10K series devices offer up to 250,000 gates, providing sufficient density, speed, and features to integrate an entire system — including multiple 32-bit buses — into a single device. FLEX 10K devices are reconfigurable, allowing 100% testing before shipment. As a result, designers do not need to generate test vectors for fault coverage purposes. In addition, designers are not required to manage inventory across different ASIC designs; FLEX 10K devices can be configured on the board to implement the specific functions required. The FLEX 10K architecture is similar to that of embedded gate arrays, the fastest-growing segment of the gate array market. Like standard gate arrays, embedded gate arrays implement general-purpose logic in a traditional "sea-of-gates" architecture. In addition, embedded gate arrays feature dedicated die areas for implementing large, specialized functions. Compared to standard gate arrays, by embedding functions in silicon, embedded gate arrays reduce die area and improve speed.

• Industry's first embedded PLD family offering programmable SOPC integration
• Embedded array for implementing macrofunctions such as efficient memory and dedicated logic functions; logic array for implementing general-purpose logic functions
• High density
• MultiVolt™ I/O interface support
• Input pins on FLEX 10KA devices are 5.0 V tolerant
• Low power consumption (typical standby current less than 0.5 mA for most devices)
• FLEX 10K and FLEX 10KA devices support PCI SIG PCI Local Bus Specification Revision 2.2
• FLEX 10KA devices include pull-up clamp diodes, selectable pin-by-pin for 3.3 V PCI compliance
• Select FLEX 10KA devices support 5.0 V PCI bus with eight or fewer loads
• Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990, consuming no device logic
• Devices manufactured with advanced process technology, operating at 3.3 V or 5.0 V supply voltage
• In-Circuit Reconfigurability (ICR) via external configuration device, intelligent controller, or JTAG port
• ClockLock™ and ClockBoost™ options for reduced clock delay/skew and clock multiplication
• Built-in low-skew clock distribution tree
• All devices 100% functionally tested; no test vectors or scan chains required
• Flexible interconnect
• FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays
• Dedicated carry chain for arithmetic functions such as fast adders, counters, and comparators (used automatically by software tools and macrofunctions)
• Dedicated cascade chain for high-speed, high-fan-in logic functions (used automatically by software tools and macrofunctions)
• Tri-state emulation for internal tri-state buses
• Up to six global clock signals and four global clear signals
• Powerful I/O pins
• Individual tri-state output enable control per pin
• Open-drain option on each I/O pin
• Programmable output slew-rate control to reduce switching noise
• Hot-socketing support on FLEX 10KA devices
• Peripheral registers for fast setup and clock-to-output delays
• Flexible package options
• Pin-compatible with other FLEX 10K devices in the same package
• FineLine BGA packages for maximum board space efficiency
• Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support via EDIF 200 and 300 netlist files, LPM, DesignWare components, Verilog HDL, VHDL, and interfaces to popular EDA tools from Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic