TI GAL22V10-20LVI

NSC E2CMOS GAL devices combine high-performance CMOS process technology with electrically erasable floating-gate technology. This programmable storage technology applied to array logic provides designers with reconfigurable logic, delivering bipolar performance at significantly reduced power consumption. The 24-pin GAL22V10 features 22 inputs and 10 programmable Output Logic Macro Cells (OLMCs), allowing users to configure each tri-state output. The architecture of each output is user-programmable, supporting registered or combinatorial operation, active-high or active-low polarity, and configurable as input, output, or bidirectional I/O. The architecture features variable product term distribution, with 8 to 16 logic product terms allocatable per output, as shown in the logic diagram. CMOS circuitry enables the GAL22V10's typical Icc of only 90mA, reducing power consumption by 50% compared to bipolar counterparts. Global synchronous preset and asynchronous reset product terms, shared across all output registers, have been added to improve system operation. Programming can be accomplished using existing industry-standard hardware and software tools. NSC guarantees a minimum of 100 erase/write cycles. A unique test circuit and reprogrammable cell allow complete AC, DC, cell, and functional testing during manufacturing. Consequently, NSC guarantees 100% field programmability for all GAL devices. In addition, an electronic signature is provided for device ID identification. A built-in security circuit provides copy protection for proprietary designs.

• High-performance E2CMOS technology
• Maximum propagation delay 15 ns
• fmax= 45 MHz with feedback
• TTL-compatible 16 mA outputs
• UltraMOS II advanced CMOS technology
• Built-in pull-up resistors on all pins
• Electrically erasable cell technology
• Reconfigurable logic
• Reprogrammable cells
• 100% tested / 100% yield guaranteed
• High-speed electrical erase (<50 ms)
• 20-year data retention
• Ten output logic macrocells
• Maximum flexibility
• Programmable output polarity
• Maximum flexibility for complex logic designs
• Variable product term allocation
• 8 to 16 product terms per output data function
• Global synchronous preset and asynchronous reset
• All registers preloadable and power-on reset
• 100% functionally testable
• Full support for National OPAL and OPALjr development software
• Security cell prevents logic duplication