Rochester Electronics TE512S32-40LI

Industry’s first complete Customizable Microcontroller platform

• High-performance, industry-standard 8051/52-compatible microcontroller (10 MIPS at 40 MHz)
• Up to 64Kbytes of on-chip, dedicated system RAM (XDATA RAM)
• Up to 2,048 Configurable System Logic (CSL) cells (roughly 40,000 gates)
• High-performance dedicated internal bus
• Advanced system debug capability
• Stand-alone operation from a single external memory (code + configuration)
• Advanced four-layer metal, 0.35μm CMOS process technology, 3.3 volt with 5 volt-tolerant I/O

Enhanced, high-performance, 8051-based microcontroller

• Binary- and instruction-set compatible with other 8051-and 8052-based devices
• 4 cycles per instruction byte provides up to 10
• Configurable, extendable architecture supports user-designed or library-provided peripherals
• Two-channel DMA controller supporting single-clock transfers
• Programmable wait-state capability
• Dual 16-bit data pointers
• Three programmable 16-bit timer/counters
• Programmable, full duplex asynchronous serial communications port
• 256-byte scratchpad RAM
• Protected programmable watchdog timer
• Programmable power-down modes, including individual PIO options
• Separate 64K address spaces for code and data
• 12 interrupt sources with three priority levels
• Embedded debugging capabilities

Embedded Configurable System Logic (CSL) matrix

• Fast, flexible CSL logic cells support combinatorial logic, arithmetic, memory, sequential, and bus functions
• Up to 2,048 CSL cells per device
• Easy, synchronous access to and from the system bus
• Programmable intercommunications network between system bus, CSL cells, and programmable I/O (PIO) pins
• Contention-free bi-directional bussing
• 8-bit read and write data, 32-bit address
• Up to 40 Mbytes/sec transfer rates
• Simple, synchronous interface to CSL peripherals, seamless connection to the microcontroller
• Multi-master bus with round-robin arbitration
• Expandable to off-chip function through memory interface unit (MIU)
• Flexible on-chip address decoders provide easy access to CSL functions
• Programmable wait-state support
• Open standard
• Forward compatible with future Triscend customizable microcontroller devices

Enhanced programmable input/output (PIO) ports

• Up to 315 user-programmable I/O per device
• Inputs, outputs, or bi-directional ports for the microcontroller, dedicated peripherals, or programmable logic peripherals
• Selectable output drive from 4 mA to 12 mA
• BusMinder circuit provides pull-up, pulldown, or weak-follower capability
• Optional input hysteresis
• Optional power-down operation, individually selectable on every pin
• Input, output and output enable flip-flops for optimal set-up and clock-to-output performance
• 5 volt tolerant inputs while operating at 3.3 volts

Memory interface unit (MIU) for flexible, glue-less interface to external memory

• Direct connect interface to an external 256Kx8 memory for initialization and code storage
• Expandable from 18 up to 32 address lines
• Variable-speed read/write timing simplifies interface design
• Access external peripherals by sharing MIU data and address pins

Two-channel advanced DMA controller

• Proxy bus masters for CSL “soft modules”
• Up to 40 Mbytes/s transfer rate (1 byte/cycle)
• Auto-initialization of channels
• Multiple addressing modes
• Software-initiated DMA requests
• Optional interrupt at end of a transfer
• Block data transfers
• CRC checking
• DMA channel request and acknowledge signals distributed to the CSL matrix

Programmable power-down modes

• Selectively disable function during powerdown
• Typically consumes less than 50 μA in full power-down mode

On-chip oscillator, crystal oscillator amplifier, and clock distribution circuitry

• 8051 reset and Customizable Microcontroller reset
• Full access to the CSI system bus and all addressable locations

Multiple in-system programming modes

• Unlimited, in-system programmability
• Byte-wide using standard FLASH, EPROM, or SRAM memories
• Serially using serial sequential-access PROM memories (SPROMs)
• Via JTAG using internal system RAM to store program code
• 'Stealth'-mode operation from internal RAM during battery-backed operation

Dedicated in-system debugging, hardware breakpoint unit

• Two breakpoint units monitor system address, data, control, and processor instruction type
• Breakpoint indicator and control from Configurable System Logic (CSL)

The Triscend E5 Customizable Microcontroller integrates, on a single device, a performance-enhanced Accelerated 8051 embedded microcontroller, a large block of SRAM, a high-speed dedicated system bus, and configurable logic, intimately connected to the processor and system bus. The E5 family is a highly integrated, fully static single-chip system optimized for embedded systems applications. Each member of the E5 family contains an identical microcontroller and set of dedicated resources. However, the size of the dedicated system RAM, the number of programmable I/O (PIO) pins, and the amount of configurable system logic grows with the larger members of the family.

The embedded high-performance 8051-based "Turbo" microcontroller is instruction-compatible with other industry-standard 8051/52-based devices, leveraging the vast software library for the 8051 architecture. While the instruction cycle for the original 8051 microcontroller is 12 clock cycles, the Accelerated 8051 microcontroller provides better performance because each instruction cycle is only four clock cycles. The result is improved performance.