RENESAS R7S910035CBG#AC0

300 MHz/450 MHz/600 MHz, MCU with Arm Cortex-R4 and -M3, on-chip FPU, 498/747/996 DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT, USB 2.0 high-speed, CAN, various communications interfaces such as an SPI multi-I/O bus controller, ΔΣ interface, safety functions, encoder interfaces, and security functions

• On-chip 32-bit Arm Cortex-R4 processor: High-speed realtime control with maximum operating frequency of 300/450/600 MHz, capable of 498/747/996 DMIPS (in operation at 300/450/600 MHz), on-chip 32-bit Arm Cortex-R4 (revision r1p4), tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes, instruction cache/data cache with ECC: 8 Kbytes per cache, high-speed interrupt, the FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single-precision and double-precision, Harvard architecture with 8-stage pipeline, supports the memory protection unit (MPU), Arm CoreSight architecture, includes support for debugging through JTAG and SWD interfaces
• On-chip 32-bit Arm Cortex-M3 processor (in products incorporating an R-IN engine): 150-MHz operating frequency, on-chip 32-bit Arm Cortex-M3 (revision r2p1), RISC Harvard architecture with 3-stage pipeline, supports the memory protection unit (MPU)
• Various communications interfaces: EtherCAT slave controller: 2 ports (optional), Ethernet MAC: 1 port (an Ethernet switch is not used) or Ethernet MAC: 1 port (an Ethernet switch to support 2 ports is used), USB 2.0 high-speed host/function: 1 channel, CAN (compliant with ISO11898-1): 2 channels (max.), SCIFA with 16-byte transmission and reception FIFOs: 5 channels, I²C bus interface: 2 channels for transfer at up to 400 kbps, RSPIa: 4 channels, SPIBSC: Provides a single interface for multi-I/O compatible serial flash memory, DMAC: 16 channels × 2 units, DMAC for the Ethernet controller: 1 channel, module operations can be started by event signals rather than by interrupt handlers, linked operation of modules is available even while the CPU is in the sleep state
• External address space: Buses for high-speed data transfer at 75 MHz (max.), support for up to 6 CS areas, 8-, 16-, or 32-bit bus space is selectable per area
• Up to 33 extended-function timers
• Four reset sources including a pin reset
• Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V (internal)
• Serial sound interface (1 channel)
• Clock functions: External clock/oscillator input frequency: 25 MHz, CPU clock frequency: Up to 300/450/600 MHz, low-speed on-chip oscillator (LOCO): 240 kHz
• Independent watchdog timer: Operated by a clock signal obtained by frequency-dividing the clock signal from the low-speed on-chip oscillator: Up to 120 kHz
• Safety functions: Register write protection, input clock oscillation stop detection, CRC, IWDTa, and A/D self-diagnosis, an error control module is incorporated to generate a pin signal output, interrupt, or internal reset in response to errors originating in the various modules
• Security functions (optional): Boot mode with security through encryption
• 12-bit A/D converters: 12 bits × 2 units (max.) (8 channels for unit 0; 16 channels for unit 1), self diagnosis, detection of analog input disconnection channel, EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE DSL-compliant interfaces, frequency-divided output from an encoder