ST SPC58NN84E7RSHBR

The SPC58 N-series microcontrollers are based on Power Architecture® technology, designed for safety-critical automotive applications requiring stringent safety standards and real-time performance. They offer high performance and real-time capability, comply with ISO 26262 ASIL D functional safety standards, and feature embedded security — suitable for high- to mid-range powertrain applications and electric vehicles.

• AEC-Q100 compliant
• 32-bit Power Architecture VLE-compatible CPU core: five enhanced master e200z4256n3 cores (dual-issue, two in lockstep pairs), with floating-point support and end-to-end ECC
• 6576 KB on-chip flash (6288 KB code flash + 288 KB data flash): read-while-write during program and erase operations, multiple blocks enabling EEPROM emulation, read-while-read between two code flash partitions
• 128 KB on-chip general-purpose SRAM (plus 384 KB within the CPU)
• 96-channel eDMA controller
• Comprehensive next-generation ASIL-D safety concept: ISO 26262 ASIL-D compliant, FCCU for fault notification collection and reaction, Memory Error Management Unit (MEMU) for memory error event collection and reporting, CRC unit
• Junction temperature range: -40°C to 165°C
• Dual-channel FlexRay controller
• Hardware Security Module (HSM)
• GTM344 General-Purpose Timer Module: intelligent complex timer module, 144 channels (48 input, 96 output), 5 programmable fine-grained multi-thread cores, 61 KB dedicated RAM, 24-bit wide channels
• Enhanced analog-to-digital conversion system: 1 monitoring 12-bit SAR ADC, 2 independent 10-bit SAR ADCs, 4 independent fast 12-bit SAR ADCs, 6 independent 16-bit Sigma-Delta ADCs (with programmable decimation filters); SAR ADC queue digital interface supporting single-channel sequencing and command sequences
• Communication interfaces: 7 LINFlexD modules, 8 Deserializing SPI (DSPI) modules, 7 Modular CAN (MCAN) modules and 1 Time-Triggered CAN (M-TTCAN) (all supporting flexible data rate ISO CAN-FD), 1 Ethernet controller (10/100 Mbps, IEEE 802.3-2008 compliant)
• Flexible power options: external regulator (1.2V core, 3.3V–5V I/O), single internal SMPS regulator
• Nexus Development Interface (NDI) compliant with IEEEISTO 5001-2003 (partial 2010 standard support)
• Boot Assist Flash (BAF) supporting factory programming via serial bootloading over asynchronous CAN or LIN/UART
• Optimized platform architecture (dedicated multi-core, local memory, etc.) for high-performance system MCU
• True ASIL-D Safety Element out of Context (SEooC) concept, leveraging hardware measures to reduce software overhead
• General-Purpose Timer Module (GTM) optimized for powertrain applications while minimizing CPU load
• Hardware sensor interfaces (SENT, PSI5)
• Enhanced communication (LFAST, Ethernet, Micro Second Bus (MSB), etc.)
• Enhanced high-dynamic signal acquisition via SD-ADC
• Innovative built-in concept enabling on-chip emulation in production-compatible packages (176-pin eLQFP and 292-pin LFBGA)
• Available in RoHS-compliant ECOPACK packaging

• Key automotive applications
• High/mid-range powertrain applications
• Electric vehicles