Infineon/CYPRESS CY22388ZXC-20
| Manufacturer | |
| MPN | CY22388ZXC-20 |
| LCSC Part # | C2957827 |
| Packaging | TSSOP-16 |
| Customer # | |
| Key Attributes | TSSOP-16 Clock Generators, PLLs, Frequency Synthesizers |
| Datasheet | Infineon/CYPRESS CY22388ZXC-20 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TSSOP-16 | |
| Features | Built-in phase-locked loop;On-chip VCO/DCO |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | Infineon/CYPRESS |
| Type | Description | |
|---|---|---|
| Packaging | TSSOP-16 | |
| Features | Built-in phase-locked loop;On-chip VCO/DCO |
Introduction
The CY22388 series devices feature one analog VCXO, four PLLs, up to eight clock outputs, and frequency selection capability. Frequency selection does not modify any PLL frequencies; instead, it allows users to choose among eight different output divider selections based on clock and package configuration. There is a programmable OE/PD# pin that can be configured as either an output enable pin or a power-down pin. The OE function can be programmed to disable a selected group of outputs when asserted low, while the remaining outputs continue to operate. A full-chip power-down asserted low disables all outputs, PLLs, and most active circuitry. The advantage of four PLLs is that a single device can generate up to four independent frequencies from a single crystal. Each PLL is independent and can be configured to generate a VCO frequency between 62.5 MHz and 250 MHz. Each PLL can then be divided down through a post-divider to generate the user-selected clock output frequency. Due to output buffer limitations, the maximum PLL frequency is reduced to 166 MHz in "divide-by-1" mode.
Features
- Fully integrated PLL
- Available in compact QFN package
- 40% smaller than 20-pin TSSOP
- 22% smaller than 16-pin TSSOP
- Selectable output frequency
- Programmable output frequency
- Output frequency range: 1 MHz to 166 MHz
- Input frequency range: 10 MHz to 30 MHz (crystal), 1 MHz to 100 MHz (external reference)
- Analog VCXO
- Available in 16/20-pin TSSOP and 32-pin QFN packages
- 3.3 V supply voltage, optional 2.5 V output buffer
Applications
- Digital set-top boxes
- DVD recorders
- Digital televisions
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.2335 | $ 0.23 |
| 200+ | $ 0.0904 | $ 18.08 |
| 500+ | $ 0.0872 | $ 43.60 |
| 1,000+ | $ 0.0856 | $ 85.60 |
Standard Packaging25/Full Tube | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TSSOP-16 | |
| Features | Built-in phase-locked loop;On-chip VCO/DCO |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | Infineon/CYPRESS |
| Type | Description | |
|---|---|---|
| Packaging | TSSOP-16 | |
| Features | Built-in phase-locked loop;On-chip VCO/DCO |
Introduction
The CY22388 series devices feature one analog VCXO, four PLLs, up to eight clock outputs, and frequency selection capability. Frequency selection does not modify any PLL frequencies; instead, it allows users to choose among eight different output divider selections based on clock and package configuration. There is a programmable OE/PD# pin that can be configured as either an output enable pin or a power-down pin. The OE function can be programmed to disable a selected group of outputs when asserted low, while the remaining outputs continue to operate. A full-chip power-down asserted low disables all outputs, PLLs, and most active circuitry. The advantage of four PLLs is that a single device can generate up to four independent frequencies from a single crystal. Each PLL is independent and can be configured to generate a VCO frequency between 62.5 MHz and 250 MHz. Each PLL can then be divided down through a post-divider to generate the user-selected clock output frequency. Due to output buffer limitations, the maximum PLL frequency is reduced to 166 MHz in "divide-by-1" mode.
Features
- Fully integrated PLL
- Available in compact QFN package
- 40% smaller than 20-pin TSSOP
- 22% smaller than 16-pin TSSOP
- Selectable output frequency
- Programmable output frequency
- Output frequency range: 1 MHz to 166 MHz
- Input frequency range: 10 MHz to 30 MHz (crystal), 1 MHz to 100 MHz (external reference)
- Analog VCXO
- Available in 16/20-pin TSSOP and 32-pin QFN packages
- 3.3 V supply voltage, optional 2.5 V output buffer
Applications
- Digital set-top boxes
- DVD recorders
- Digital televisions
C2957827 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

