Infineon/CYPRESS CY23FP12OC

CY23FP12 is a high-performance, fully field-programmable 200 MHz zero-delay buffer designed for high-speed clock distribution. The integrated PLL is designed for low jitter and optimized noise rejection. These parameters are critical for reference clock distribution in systems using high-performance ASICs and microprocessors. The CY23FP12 is fully programmable via production or prototype programmers, enabling users to define application-specific zero-delay buffers with custom input and output dividers, feedback topology (internal/external), output inversion, and output drive strength. For additional flexibility, users can mix and match multiple features and assign specific feature sets to any of four possible S1-S2 control bit combinations. This capability allows four distinct personalities to be implemented on a single programmed device, selectable via the S1-S2 bits. The CY23FP12 also features a proprietary automatic power-down circuit that shuts down the device upon REF loss, resulting in current consumption of less than 50 μA. The CY23FP12 provides twelve outputs divided into two banks with independent power pins, which can be independently connected to 2.5V or 3.3V supply rails. The optional reference input is a fault-tolerant feature that allows glitch-free switching to a secondary clock source upon REFSEL assertion/deassertion.

• Fully field programmable
• Input and output dividers
• Inverting/non-inverting outputs
• PLL or fanout buffer configuration
• 10 MHz to 200 MHz operating range
• Separate 2.5V or 3.3V outputs
• Two LVCMOS reference inputs
• Twelve low-skew outputs
• 35 ps typical output-to-output skew (same frequency)
• 110 ps typical cycle-to-cycle jitter (same frequency)
• Tri-state outputs
• Less than 50 μA shutdown current
• Spread Aware
• 28-pin SSOP
• 3.3V operation
• Industrial temperature available