Infineon/CYPRESS CY7C1019BV33-15ZC

CY7C1019BV33/CY7C1018BV33 is a high-performance CMOS SRAM organized as 131,072 words × 8 bits. Memory expansion is easily achieved through active-low chip enable (CE), active-low output enable (OE), and three-state drivers. The device features automatic power-down, which significantly reduces power consumption when deselected. To write data to the device, CE and write enable (WE) inputs are driven low, causing data on the 8 I/O pins (I/O₀–I/O₇) to be written to the location specified by the address pins (A₀–A₁₆). To read data from the device, CE and OE are driven low while WE is held high, causing the contents of the memory cell specified by the address pins to appear on the I/O pins. The 8 I/O pins (I/O₀–I/O₇) are in a high-impedance state when the device is deselected (CE high), the output is disabled (OE high), or a write operation is in progress (CE low and WE low). CY7C1019BV33 is available in standard 32-pin TSOP II and 400-mil wide packages; CY7C1018BV33 is available in a standard 300-mil wide package.

• Access time tₐₐ = 10 ns
• High speed
• CMOS technology for optimized speed/power performance
• Center power/ground pin layout
• Automatic power-down when deselected
• Easy memory expansion via CE and OE options
• Functionally equivalent to CY7C1019V33 and/or CY7C1018V33