Infineon/CYPRESS CY7C1325A-117AC

The Cypress synchronous burst SRAM family employs a high-speed, low-power CMOS design using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-value resistors. The CY7C1325A/GVT71256E18 SRAM integrates 262,144×18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are registered by a positive edge-triggered clock input (CLK). Synchronous inputs include all addresses, all data inputs, address pipeline chip enable (CE), depth expansion chip selects (CE2 and CE2), burst control inputs (ADSC, ADSP, and ADV), write enables (WEL, WEH, and BWE), and global write (GW). Asynchronous inputs include output enable (OE), burst mode control (MODE), and sleep mode control (ZZ). Data outputs (DQ) enabled by OE are also asynchronous. Addresses and chip selects are registered via the address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be generated internally under control of the burst advance pin (ADV). Addresses, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. Write cycle width is selectable from 1 to 4 bytes via the write control inputs. Individual byte writes allow writing to a single byte. WEL controls DQ1–DQ8 and DQP1; WEH controls DQ9–DQ16 and DQP2. WEL and WEH are valid only when BWE is LOW. When GW is LOW, all bytes are written. The CY7C1325A/GVT71256E18 operates from a +3.3V supply, with all outputs using a +2.5V supply. All inputs and outputs are compliant with JEDEC standard JESD8-5. This device is well suited for 486, Pentium, 680x0, and Power-PC systems, as well as systems that benefit from a wide synchronous data bus.

• Fast access time: 7.5 and 8 ns
• Fast clock speed: 117 and 100 MHz
• High-performance 2-1-1 access rate
• Fast OE access time: 4.0 ns
• 3.3V ±5% and +10% power supply
• 2.5V or 3.3V I/O power supply
• Inputs 5V-tolerant except I/O
• Clamp diodes to VSSQ on all inputs and outputs
• Common data input and data output
• Byte write enable and global write control
• Three chip selects for depth expansion and address pipelining
• Address, data, and control registers
• Internal self-timed write cycle
• Burst control pin (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• Low-profile 119-pin 14mm x 22mm BGA and 100-pin TQFP packages

• 486 systems
• Pentium systems
• 680x0 systems
• Power PC systems
• Wide synchronous data bus systems