Infineon/CYPRESS CY7C1339A-66AC

The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operations. All synchronous inputs are strobed by registers controlled by a positive edge-triggered clock input (CLK). Synchronous inputs include all addresses, all data inputs, address pipeline chip select (CE1̄), depth expansion chip selects (CE2̄ and CE3̄), burst control inputs (ADSC̄, ADSP̄, and ADV̄), write enables (BW[A:D]̄ and BWĒ), and global write (GW̄). Asynchronous inputs include output enable (OĒ) and the ZZ pin. Addresses and chip selects are registered on the rising edge of the clock when the Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) is activated. Subsequent burst addresses can be generated internally under control of the Advance pin (ADV̄). Addresses, data inputs, and write controls are registered on-chip to initiate self-timed write cycles. The device supports byte write operations. The CY7C1339F is powered by a +3.3V core supply, and all outputs can be powered by either a +2.5V or +3.3V supply. All inputs and outputs are compatible with JEDEC standard JESD8-5.

• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core supply, 2.5V / 3.3V I/O operation
• Fast clock-to-output times ranging from 2.6ns (250MHz devices) to 4.5ns (100MHz devices)
• High-performance 3-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in standard 100-pin TQFP and 119-ball BGA packages
• "ZZ" sleep mode option available