Infineon/CYPRESS CY7C1351B-117AC

CY7C1351B is a 3.3V, 128K×36 synchronous flow-through burst SRAM designed to support unlimited consecutive read and write operations without wait states. Equipped with advanced No Bus Latency (NoBL™) logic, it transfers data every clock cycle to enable continuous read/write operations, significantly improving SRAM data throughput — particularly well-suited for systems requiring frequent read-to-write transitions. It is pin and function compatible with ZBT SRAM IDT71V547, MT55L128L36F, and MCM63Z737. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal; when CEN is inactive, operation is suspended and the previous clock cycle is extended. The maximum access delay from the clock rising edge is 7.5 ns (117-MHz device). Write operations are controlled by four Byte Write Select (BWS[3:0]̄) and Write Enable (WE) inputs; all write operations are performed through an on-chip synchronous self-timed write circuit. Three synchronous chip enables (C̄E̅1̄, CE2, C̄E̅3̄) and one asynchronous Output Enable (OE) facilitate memory bank selection and output tri-state control. To prevent bus contention, the output drivers synchronously enter tri-state during the data portion of a write sequence.

• Pin-compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737
• 66-MHz bus operation support, zero wait states, data transfer every clock cycle
• Internal self-timed output buffer control, no OE required
• Registered inputs for flow-through operation
• Byte write capability
• 128K×36 universal I/O architecture
• Single 3.3V supply
• Fast clock-to-output time: 7.5 ns (117-MHz device); 8.5 ns (100-MHz device); 11.0 ns (66-MHz device); 12.0 ns (50-MHz device); 14.0 ns (40-MHz device)
• Clock enable (CEN) pin for suspend operation
• Synchronous self-timed write
• Asynchronous output enable
• Standard 100 TQFP and 119 BGA packages
• Burst capability: linear or interleaved burst order
• Low standby power consumption