Infineon/CYPRESS CY7C1361A-133AJC

Cypress synchronous burst SRAM families are fabricated using high-speed, low-power CMOS technology with an advanced triple-polysilicon, double-metal process. Each memory cell consists of four transistors and two high-value resistors. The GVT71256B36/CY7C1361A and GVT71512B18/CY7C1363A SRAMs integrate 262,144×36 and 524,288×18 SRAM cells respectively, along with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are registered by a positive edge-triggered clock input (CLK). Synchronous inputs include all addresses, all data inputs, address pipeline chip enable (CE), depth expansion chip enable (CE₂), burst control inputs (ADSC, ADSP, and ADV), byte write enables (BWa, BWb, BWc, BWd, and BWE), and global write (GW). Asynchronous inputs include output enable (OE) and burst mode control (MODE). Data outputs (Q) are enabled by OE and are also asynchronous. Addresses and chip selects are registered through the address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be generated internally under control of the burst advance pin (ADV). Addresses, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. The write cycle width is selectable from 1 to 4 bytes via the write control inputs. For B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions, four pins are used to implement JTAG test functionality. The GVT71256B36 and GVT71512B18 operate from a +3.3V supply, with all inputs and outputs compatible with LVTTL.

• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
• Fast clock speeds: 150, 133, 117, and 100 MHz
• 1 ns setup time and hold time
• Fast OE access times: 3.5 ns and 4.0 ns
• 3.3V -5% and +10% power supply
• 3.3V or 2.5V I/O power supply
• 5V-tolerant inputs except I/O
• Clamp diodes on all inputs and outputs to VSS
• Common data input and data output
• Byte write enable and global write control
• Multiple chip selects for depth expansion: TA(GVTI)/A(CY) package versions have three chip selects; B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions have two chip selects
• Address pipelining capability
• Address, data, and control registers
• Internal self-timed write cycle
• Burst control pin (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package versions
• Thin 119-bump, 14 mm x 22 mm PBGA and 100-pin TQFP packages